公开(公告)号：US08717066B2

公开(公告)日：2014-05-06

申请号：US13614235

申请日：2012-09-13

申请人： Naoya Ohnishi ,  Hiroshi Nakatani ,  Yoshito Sameda ,  Jun Takehara ,  Makoto Toko

发明人： Naoya Ohnishi ,  Hiroshi Nakatani ,  Yoshito Sameda ,  Jun Takehara ,  Makoto Toko

IPC分类号： H03K5/22

CPC分类号： H03K5/19 ,  G06F1/04

摘要： A clock diagnosis circuit includes: a delay circuit to delay the clock by a prescribed time which is not more than the clock pulse width; an integral multiplication delay circuit to delay a delayed clock outputted from the delay circuit by a prescribed number of cycles; a first exclusive OR circuit to encode the clock using the delayed clock; a second exclusive OR circuit to decode an output of the first exclusive OR circuit using an output of the integral multiplication delay circuit; and a comparison circuit to compare the clock with an output of the second exclusive OR circuit to thereby detect a malfunction of the clock.

摘要翻译： 时钟诊断电路包括：将时钟延迟规定时间的延迟电路，该规定时间不大于时钟脉冲宽度; 整数乘法延迟电路，用于将从延迟电路输出的延迟时钟延迟预定数量的周期; 使用延迟时钟对时钟进行编码的第一异或电路; 使用积分乘法延迟电路的输出来对第一异或电路的输出进行解码的第二异或电路; 以及比较电路，用于将时钟与第二异或电路的输出进行比较，从而检测时钟的故障。

公开(公告)号：US08516310B2

公开(公告)日：2013-08-20

申请号：US13025499

申请日：2011-02-11

申请人： Naoya Ohnishi ,  Hiroshi Nakatani ,  Yoshito Sameda

发明人： Naoya Ohnishi ,  Hiroshi Nakatani ,  Yoshito Sameda

IPC分类号： G06F11/00

CPC分类号： G11C29/44 ,  G06F12/0804 ,  G11C2029/0401 ,  G11C2029/0409

摘要： The embodiments provide a failure diagnosis method for a main memory in an information processing device equipped with a write-back cache. According to the method, an application program stored in the main memory is divided by the storage size of write-back cache, and the regions are stored in advance. Then, a read signal from the main memory to the write-back cache is detected. It is determined whether the region corresponding to the read signal has yet to be diagnosed. If the region has yet to be diagnosed, a command to diagnose failure of the region is issued. If a write signal (write back) to a particular region is detected during the diagnosis of the particular region, the diagnosis of the particular region is stopped. Thus, the failure diagnosis of the main memory is executed in parallel with the execution of the application program.

摘要翻译： 这些实施例提供了配备有回写高速缓存的信息处理设备中的主存储器的故障诊断方法。 根据该方法，将存储在主存储器中的应用程序除以回写高速缓存的存储大小，并且预先存储区域。 然后，检测从主存储器到写回高速缓存的读信号。 确定与读取信号相对应的区域是否尚未被诊断。 如果该地区尚未确诊，则会发出诊断该地区失败的指令。 如果在特定区域的诊断期间检测到特定区域的写入信号（回写），则特定区域的诊断被停止。 因此，与应用程序的执行并行地执行主存储器的故障诊断。

公开(公告)号：US08762788B2

公开(公告)日：2014-06-24

申请号：US13206898

申请日：2011-08-10

申请人： Hiroshi Nakatani ,  Naoya Ohnishi ,  Makoto Toko ,  Motohiko Okabe

发明人： Hiroshi Nakatani ,  Naoya Ohnishi ,  Makoto Toko ,  Motohiko Okabe

IPC分类号： G06F11/14

CPC分类号： G05B9/03 ,  G05B19/0428 ,  G05B2219/24187

摘要： A redundancy control system and method of transmitting computational data are provided, for detection of transmission errors and failure diagnosis, including generating first computational data and generating first generated data using a first generation algorithm for error detection; generating second computational data and generating second generated data using a second generation algorithm for error detection; comparing the first/second computational data; transmitting transmission data including coincident computational data and the first/second generated data; generating, in the receiving device, computational data and third/fourth generated data from preset first/second generation algorithms; and comparing the first/third generated data and the first/third generated data, and detecting the presence or absence of an error in the received computational data.

摘要翻译： 提供了一种发送计算数据的冗余控制系统和方法，用于检测传输错误和故障诊断，包括生成第一计算数据，并使用第一代算法生成第一生成数据进行错误检测; 产生第二计算数据并使用用于错误检测的第二代算法产生第二生成数据; 比较第一/第二计算数据; 发送包括一致的计算数据和所述第一/第二生成数据的传输数据; 在接收装置中从预设的第一/第二代算法生成计算数据和第三/第四生成数据; 以及比较所述第一/第三生成数据和所述第一/第三生成数据，并且检测所接收的计算数据中是否存在错误。

公开(公告)号：US20120047406A1

公开(公告)日：2012-02-23

申请号：US13206898

申请日：2011-08-10

申请人： Hiroshi NAKATANI ,  Naoya Ohnishi ,  Makoto Toko ,  Motohiko Okabe

发明人： Hiroshi NAKATANI ,  Naoya Ohnishi ,  Makoto Toko ,  Motohiko Okabe

IPC分类号： G06F11/07

CPC分类号： G05B9/03 ,  G05B19/0428 ,  G05B2219/24187

摘要： A method of transmitting computational data comprising: a step of generating first computational data and generating first generated data using a first generation algorithm for error detection on return; a step of generating second computational data and generating second generated data using a second generation algorithm for error detection; a step of mutually comparing the first/second computational data; a step of transmitting transmission data including coincident computational data and first/second generated data; in the receiving device, a step of generating computational data and third/fourth generated data from preset first/second generation algorithms; and a step of comparing the first/third generated data and the first/third generated data, and detecting error in the received computational data.

摘要翻译： 一种发送计算数据的方法，包括：生成第一计算数据并使用第一生成算法生成第一生成数据的步骤，用于返回时的错误检测; 使用用于错误检测的第二代算法产生第二计算数据并产生第二生成数据的步骤; 相互比较第一/第二计算数据的步骤; 发送包括一致的计算数据和第一/第二生成数据的发送数据的步骤; 在接收装置中，从预设的第一/第二代算法生成计算数据和第三/第四生成数据的步骤; 以及比较第一/第三生成数据和第一/第三生成数据以及检测接收到的计算数据中的错误的步骤。

公开(公告)号：US08559734B2

公开(公告)日：2013-10-15

申请号：US13023018

申请日：2011-02-08

申请人： Naoya Ohnishi ,  Tomoo Yamakage ,  Tomoya Kodama ,  Hiroaki Fukui

发明人： Naoya Ohnishi ,  Tomoo Yamakage ,  Tomoya Kodama ,  Hiroaki Fukui

IPC分类号： G06K9/36

CPC分类号： H04N19/40 ,  H04N19/184 ,  H04N19/61

摘要： In one embodiment, an image encoding apparatus converts bit depth of an input image formed of a plurality of pixels each having an N bit depth into an (N+M) bit depth larger than N bit depth by M bits. An adaptive bit depth converter converts the bit depth of each pixel of the decoded image of the (N+M) bits into the N bits selectively using one of a plurality of conversion systems. The converted image of the N bit depth is stored in a frame memory as a reference image. The bit depth of each pixel of the reference image of the N bit depth read out from the frame memory is converted into the (N+M) bit depth larger than the N bit depth by M bits in accordance with the conversion system by a pixel bit depth inverse converter.

摘要翻译： 在一个实施例中，图像编码装置将由具有N比特深度的多个像素形成的输入图像的比特深度转换为大于N比特深度（N + M）比特深度M比特。 自适应位深度转换器使用多个转换系统之一选择性地将（N + M）位的解码图像的每个像素的比特深度转换成N比特。 将N位深度的转换图像作为参考图像存储在帧存储器中。 从帧存储器读出的N比特深度的参考图像的每个像素的比特深度根据转换系统被转换成比N比特深度大的比特深度M比特 位深度逆变换器。