公开(公告)号：US08638583B2

公开(公告)日：2014-01-28

申请号：US13621078

申请日：2012-09-15

申请人： Naoya Watanabe ,  Isamu Hayashi ,  Teruhiko Amano ,  Fukashi Morishita ,  Kenji Yoshinaga ,  Mihoko Akiyama ,  Shinya Miyazaki ,  Masakazu Ishibashi ,  Katsumi Dosaka

发明人： Naoya Watanabe ,  Isamu Hayashi ,  Teruhiko Amano ,  Fukashi Morishita ,  Kenji Yoshinaga ,  Mihoko Akiyama ,  Shinya Miyazaki ,  Masakazu Ishibashi ,  Katsumi Dosaka

IPC分类号： G11C15/00 ,  G11C15/04 ,  G11C7/14 ,  G11C7/06 ,  G11C7/12 ,  G11C7/22

CPC分类号： G11C15/043 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C7/22 ,  G11C15/04 ,  G11C15/046

摘要： An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.

摘要翻译： 包括存储数据位的单位单元的多个比特的条目耦合到匹配线。 匹配线具有一个充电电流，该充电电流的限制电流值小于在一个条目中以一位未命中状态流动的匹配线电流，但大于在一个条目中以全位匹配状态流动的匹配线电流 。 匹配线的预充电电压电平被限制为电源电压的一半或更小的电压电平。 可以减少内容可寻址存储器的搜索周期中的功耗，并且可以提高搜索操作速度。

公开(公告)号：US08310852B2

公开(公告)日：2012-11-13

申请号：US13419217

申请日：2012-03-13

申请人： Naoya Watanabe ,  Isamu Hayashi ,  Teruhiko Amano ,  Fukashi Morishita ,  Kenji Yoshinaga ,  Mihoko Akiyama ,  Shinya Miyazaki ,  Masakazu Ishibashi ,  Katsumi Dosaka

发明人： Naoya Watanabe ,  Isamu Hayashi ,  Teruhiko Amano ,  Fukashi Morishita ,  Kenji Yoshinaga ,  Mihoko Akiyama ,  Shinya Miyazaki ,  Masakazu Ishibashi ,  Katsumi Dosaka

IPC分类号： G11C15/00 ,  G11C15/04 ,  G11C7/14 ,  G11C7/06 ,  G11C7/12 ,  G11C7/22

CPC分类号： G11C15/043 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C7/22 ,  G11C15/04 ,  G11C15/046

摘要： An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.

公开(公告)号：US20070247885A1

公开(公告)日：2007-10-25

申请号：US11730969

申请日：2007-04-05

申请人： Naoya Watanabe ,  Isamu Hayashi ,  Teruhiko Amano ,  Fukashi Morishita ,  Kenji Yoshinaga ,  Mihoko Akiyama ,  Shinya Miyazaki ,  Masakazu Ishibashi ,  Katsumi Dosaka

发明人： Naoya Watanabe ,  Isamu Hayashi ,  Teruhiko Amano ,  Fukashi Morishita ,  Kenji Yoshinaga ,  Mihoko Akiyama ,  Shinya Miyazaki ,  Masakazu Ishibashi ,  Katsumi Dosaka

IPC分类号： G11C15/00

CPC分类号： G11C15/043 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C7/22 ,  G11C15/04 ,  G11C15/046

摘要： An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.

摘要翻译： 包括存储数据位的单位单元的多个比特的条目耦合到匹配线。 匹配线具有一个充电电流，该充电电流的限制电流值小于在一个条目中以一位未命中状态流动的匹配线电流，但大于在一个条目中以全位匹配状态流动的匹配线电流 。 匹配线的预充电电压电平被限制为电源电压的一半或更小的电压电平。 可以减少内容可寻址存储器的搜索周期中的功耗，并且可以提高搜索操作速度。

公开(公告)号：US20130010513A1

公开(公告)日：2013-01-10

申请号：US13621078

申请日：2012-09-15

申请人： Naoya WATANABE ,  Isamu Hayashi ,  Teruhiko Amano ,  Fukashi Morishita ,  Kenji Yoshinaga ,  Mihoko Akiyama ,  Shinya Miyazaki ,  Masakazu Ishibashi ,  Katsumi Dosaka

发明人： Naoya WATANABE ,  Isamu Hayashi ,  Teruhiko Amano ,  Fukashi Morishita ,  Kenji Yoshinaga ,  Mihoko Akiyama ,  Shinya Miyazaki ,  Masakazu Ishibashi ,  Katsumi Dosaka

IPC分类号： G11C15/00

CPC分类号： G11C15/043 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C7/22 ,  G11C15/04 ,  G11C15/046

摘要： An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.

公开(公告)号：US08164934B2

公开(公告)日：2012-04-24

申请号：US12720561

申请日：2010-03-09

申请人： Naoya Watanabe ,  Isamu Hayashi ,  Teruhiko Amano ,  Fukashi Morishita ,  Kenji Yoshinaga ,  Mihoko Akiyama ,  Shinya Miyazaki ,  Masakazu Ishibashi ,  Katsumi Dosaka

发明人： Naoya Watanabe ,  Isamu Hayashi ,  Teruhiko Amano ,  Fukashi Morishita ,  Kenji Yoshinaga ,  Mihoko Akiyama ,  Shinya Miyazaki ,  Masakazu Ishibashi ,  Katsumi Dosaka

IPC分类号： G11C15/00 ,  G11C15/04 ,  G11C7/14 ,  G11C7/06 ,  G11C7/12 ,  G11C7/22

CPC分类号： G11C15/043 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C7/22 ,  G11C15/04 ,  G11C15/046

摘要： An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.

摘要翻译： 包括存储数据位的单位单元的多个比特的条目耦合到匹配线。 匹配线具有一个充电电流，该充电电流的限制电流值小于在一个条目中以一位未命中状态流动的匹配线电流，但大于在一个条目中以全位匹配状态流动的匹配线电流 。 匹配线的预充电电压电平被限制为电源电压的一半或更小的电压电平。 可以减少内容可寻址存储器的搜索周期中的功耗，并且可以增加搜索操作速度。

公开(公告)号：US08451678B2

公开(公告)日：2013-05-28

申请号：US13080114

申请日：2011-04-05

申请人： Mihoko Akiyama ,  Futoshi Igaue ,  Kenji Yoshinaga ,  Masashi Matsumura ,  Fukashi Morishita

发明人： Mihoko Akiyama ,  Futoshi Igaue ,  Kenji Yoshinaga ,  Masashi Matsumura ,  Fukashi Morishita

IPC分类号： G11C5/14

CPC分类号： G05F1/468 ,  G11C5/025 ,  G11C5/147

摘要： A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.

摘要翻译： 半导体集成电路器件具有设置在每个用于六个存储器宏的电源电路单元的负电压产生电路。 因此，相对于负电压的变化的响应增加。 在待机模式下，通过开关电路连接六个存储器宏的负电压供给线，并且仅在六个电源电路单元的六个负电压产生电路中仅一个电源电路单元的负电压产生电路 活性。 因此，可以防止待机电流的增加。

公开(公告)号：US08004923B2

公开(公告)日：2011-08-23

申请号：US12683838

申请日：2010-01-07

申请人： Mihoko Akiyama ,  Futoshi Igaue ,  Kenji Yoshinaga ,  Masashi Matsumura ,  Fukashi Morishita

发明人： Mihoko Akiyama ,  Futoshi Igaue ,  Kenji Yoshinaga ,  Masashi Matsumura ,  Fukashi Morishita

IPC分类号： G11C5/14

CPC分类号： G05F1/468 ,  G11C5/025 ,  G11C5/147

摘要： A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.

摘要翻译： 半导体集成电路器件具有设置在每个用于六个存储器宏的电源电路单元的负电压产生电路。 因此，相对于负电压的变化的响应增加。 在待机模式下，通过开关电路连接六个存储器宏的负电压供给线，并且仅在六个电源电路单元的六个负电压产生电路中仅一个电源电路单元的负电压产生电路 活性。 因此，可以防止待机电流的增加。

公开(公告)号：US07656736B2

公开(公告)日：2010-02-02

申请号：US11717717

申请日：2007-03-14

申请人： Mihoko Akiyama ,  Futoshi Igaue ,  Kenji Yoshinaga ,  Masashi Matsumura ,  Fukashi Morishita

发明人： Mihoko Akiyama ,  Futoshi Igaue ,  Kenji Yoshinaga ,  Masashi Matsumura ,  Fukashi Morishita

IPC分类号： G11C5/14

CPC分类号： G05F1/468 ,  G11C5/025 ,  G11C5/147

摘要： A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.

摘要翻译： 半导体集成电路器件具有设置在每个用于六个存储器宏的电源电路单元的负电压产生电路。 因此，相对于负电压的变化的响应增加。 在待机模式下，通过开关电路连接六个存储器宏的负电压供给线，并且仅在六个电源电路单元的六个负电压产生电路中仅一个电源电路单元的负电压产生电路 活性。 因此，可以防止待机电流的增加。

公开(公告)号：US20110182131A1

公开(公告)日：2011-07-28

申请号：US13080114

申请日：2011-04-05

申请人： Mihoko Akiyama ,  Futoshi Igaue ,  Kenji Yoshinaga ,  Masashi Matsumura ,  Fukashi Morishita

发明人： Mihoko Akiyama ,  Futoshi Igaue ,  Kenji Yoshinaga ,  Masashi Matsumura ,  Fukashi Morishita

IPC分类号： G11C5/14

CPC分类号： G05F1/468 ,  G11C5/025 ,  G11C5/147

摘要： A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.

摘要翻译： 半导体集成电路器件具有设置在每个用于六个存储器宏的电源电路单元的负电压产生电路。 因此，相对于负电压的变化的响应增加。 在待机模式下，通过开关电路连接六个存储器宏的负电压供给线，并且仅在六个电源电路单元的六个负电压产生电路中仅一个电源电路单元的负电压产生电路 活性。 因此，可以防止待机电流的增加。

公开(公告)号：US07408818B2

公开(公告)日：2008-08-05

申请号：US11703672

申请日：2007-02-08

申请人： Kenji Yoshinaga ,  Masashi Matsumura ,  Futoshi Igaue ,  Mihoko Akiyama ,  Fukashi Morishita

发明人： Kenji Yoshinaga ,  Masashi Matsumura ,  Futoshi Igaue ,  Mihoko Akiyama ,  Fukashi Morishita

IPC分类号： G11C11/34

CPC分类号： G11C29/48 ,  G11C29/12 ,  G11C29/12005

摘要： A semiconductor device has a first operation mode and a second operation mode in which power supply with a higher voltage value than that in the first operation mode is provided. The semiconductor device includes a memory portion having memory cells for storing data and a power supply circuit portion supplying a first voltage and a second voltage to the memory portion. The memory portion writes or reads data to or from the memory cells based on the first voltage and the second voltage, and the power supply circuit portion provides a smaller voltage difference between the first voltage and the second voltage in the second operation mode as compared with the voltage difference in the first operation mode.

摘要翻译： 半导体器件具有第一操作模式和第二操作模式，其中提供具有比第一操作模式中更高的电压值的电源。 半导体器件包括具有用于存储数据的存储单元的存储器部分和向存储器部分提供第一电压和第二电压的电源电路部分。 存储器部分基于第一电压和第二电压将数据写入或从存储器单元读取数据，并且电源电路部分在第二操作模式中在第一电压和第二电压之间提供较小的电压差，与第 在第一操作模式下的电压差。