公开(公告)号：US08638583B2

公开(公告)日：2014-01-28

申请号：US13621078

申请日：2012-09-15

申请人： Naoya Watanabe ,  Isamu Hayashi ,  Teruhiko Amano ,  Fukashi Morishita ,  Kenji Yoshinaga ,  Mihoko Akiyama ,  Shinya Miyazaki ,  Masakazu Ishibashi ,  Katsumi Dosaka

发明人： Naoya Watanabe ,  Isamu Hayashi ,  Teruhiko Amano ,  Fukashi Morishita ,  Kenji Yoshinaga ,  Mihoko Akiyama ,  Shinya Miyazaki ,  Masakazu Ishibashi ,  Katsumi Dosaka

IPC分类号： G11C15/00 ,  G11C15/04 ,  G11C7/14 ,  G11C7/06 ,  G11C7/12 ,  G11C7/22

CPC分类号： G11C15/043 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C7/22 ,  G11C15/04 ,  G11C15/046

摘要： An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.

摘要翻译： 包括存储数据位的单位单元的多个比特的条目耦合到匹配线。 匹配线具有一个充电电流，该充电电流的限制电流值小于在一个条目中以一位未命中状态流动的匹配线电流，但大于在一个条目中以全位匹配状态流动的匹配线电流 。 匹配线的预充电电压电平被限制为电源电压的一半或更小的电压电平。 可以减少内容可寻址存储器的搜索周期中的功耗，并且可以提高搜索操作速度。

公开(公告)号：US08310852B2

公开(公告)日：2012-11-13

申请号：US13419217

申请日：2012-03-13

申请人： Naoya Watanabe ,  Isamu Hayashi ,  Teruhiko Amano ,  Fukashi Morishita ,  Kenji Yoshinaga ,  Mihoko Akiyama ,  Shinya Miyazaki ,  Masakazu Ishibashi ,  Katsumi Dosaka

发明人： Naoya Watanabe ,  Isamu Hayashi ,  Teruhiko Amano ,  Fukashi Morishita ,  Kenji Yoshinaga ,  Mihoko Akiyama ,  Shinya Miyazaki ,  Masakazu Ishibashi ,  Katsumi Dosaka

IPC分类号： G11C15/00 ,  G11C15/04 ,  G11C7/14 ,  G11C7/06 ,  G11C7/12 ,  G11C7/22

CPC分类号： G11C15/043 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C7/22 ,  G11C15/04 ,  G11C15/046

摘要： An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.

公开(公告)号：US20070247885A1

公开(公告)日：2007-10-25

申请号：US11730969

申请日：2007-04-05

申请人： Naoya Watanabe ,  Isamu Hayashi ,  Teruhiko Amano ,  Fukashi Morishita ,  Kenji Yoshinaga ,  Mihoko Akiyama ,  Shinya Miyazaki ,  Masakazu Ishibashi ,  Katsumi Dosaka

发明人： Naoya Watanabe ,  Isamu Hayashi ,  Teruhiko Amano ,  Fukashi Morishita ,  Kenji Yoshinaga ,  Mihoko Akiyama ,  Shinya Miyazaki ,  Masakazu Ishibashi ,  Katsumi Dosaka

IPC分类号： G11C15/00

CPC分类号： G11C15/043 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C7/22 ,  G11C15/04 ,  G11C15/046

摘要： An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.

摘要翻译： 包括存储数据位的单位单元的多个比特的条目耦合到匹配线。 匹配线具有一个充电电流，该充电电流的限制电流值小于在一个条目中以一位未命中状态流动的匹配线电流，但大于在一个条目中以全位匹配状态流动的匹配线电流 。 匹配线的预充电电压电平被限制为电源电压的一半或更小的电压电平。 可以减少内容可寻址存储器的搜索周期中的功耗，并且可以提高搜索操作速度。

公开(公告)号：US20130010513A1

公开(公告)日：2013-01-10

申请号：US13621078

申请日：2012-09-15

申请人： Naoya WATANABE ,  Isamu Hayashi ,  Teruhiko Amano ,  Fukashi Morishita ,  Kenji Yoshinaga ,  Mihoko Akiyama ,  Shinya Miyazaki ,  Masakazu Ishibashi ,  Katsumi Dosaka

发明人： Naoya WATANABE ,  Isamu Hayashi ,  Teruhiko Amano ,  Fukashi Morishita ,  Kenji Yoshinaga ,  Mihoko Akiyama ,  Shinya Miyazaki ,  Masakazu Ishibashi ,  Katsumi Dosaka

IPC分类号： G11C15/00

CPC分类号： G11C15/043 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C7/22 ,  G11C15/04 ,  G11C15/046

摘要： An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.

公开(公告)号：US08164934B2

公开(公告)日：2012-04-24

申请号：US12720561

申请日：2010-03-09

申请人： Naoya Watanabe ,  Isamu Hayashi ,  Teruhiko Amano ,  Fukashi Morishita ,  Kenji Yoshinaga ,  Mihoko Akiyama ,  Shinya Miyazaki ,  Masakazu Ishibashi ,  Katsumi Dosaka

发明人： Naoya Watanabe ,  Isamu Hayashi ,  Teruhiko Amano ,  Fukashi Morishita ,  Kenji Yoshinaga ,  Mihoko Akiyama ,  Shinya Miyazaki ,  Masakazu Ishibashi ,  Katsumi Dosaka

IPC分类号： G11C15/00 ,  G11C15/04 ,  G11C7/14 ,  G11C7/06 ,  G11C7/12 ,  G11C7/22

CPC分类号： G11C15/043 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C7/22 ,  G11C15/04 ,  G11C15/046

摘要： An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.

摘要翻译： 包括存储数据位的单位单元的多个比特的条目耦合到匹配线。 匹配线具有一个充电电流，该充电电流的限制电流值小于在一个条目中以一位未命中状态流动的匹配线电流，但大于在一个条目中以全位匹配状态流动的匹配线电流 。 匹配线的预充电电压电平被限制为电源电压的一半或更小的电压电平。 可以减少内容可寻址存储器的搜索周期中的功耗，并且可以增加搜索操作速度。

公开(公告)号：US06418067B1

公开(公告)日：2002-07-09

申请号：US09592454

申请日：2000-06-09

申请人： Naoya Watanabe ,  Akira Yamazaki ,  Kazutami Arimoto ,  Takeshi Fujino ,  Isamu Hayashi ,  Hideyuki Noda

发明人： Naoya Watanabe ,  Akira Yamazaki ,  Kazutami Arimoto ,  Takeshi Fujino ,  Isamu Hayashi ,  Hideyuki Noda

IPC分类号： G11C700

CPC分类号： G11C29/78 ,  G11C11/4076 ,  G11C29/846

摘要： Read data line pairs, write data line pairs, a spare read data line pair, and a spare write data line pair are provided extending in the column direction over a memory cell array. Spare bit repair is performed by replacing a data line pair. Column redundancy control circuit changes the timing for outputting the result of spare determination for a data write mode and for a data read mode. A semiconductor memory device suitable for merging with a logic and capable of reducing the current consumption and achieving a higher operation frequency is provided.

摘要翻译： 读取数据线对，写入数据线对，备用读取数据线对和备用写入数据线对，提供在存储单元阵列上的列方向上延伸。 通过替换数据线对执行备用位修复。 列冗余控制电路改变用于输出数据写入模式和数据读取模式的备用确定结果的定时。 提供一种适于与逻辑并入并能够降低电流消耗并实现更高操作频率的半导体存储器件。

公开(公告)号：US5926630A

公开(公告)日：1999-07-20

申请号：US788836

申请日：1997-01-27

申请人： Isamu Hayashi

发明人： Isamu Hayashi

IPC分类号： G06F13/00 ,  G06F13/38 ,  H04Q3/00

CPC分类号： G06F13/385

摘要： The object of the present invention is to obtain a communication device which improves latency and throughput in data transfer processing by reducing the number of accesses to a local bus. A bus interface 1a receives an user data from an AALLSI 4, and, when a host bus cannot be occupied, temporarily stores the user data in a data receiving buffer area 11. The capacity of the data receiving buffer area 11 in the bus interface 1a is set so as not to be full during normal data processing.

摘要翻译： 本发明的目的是获得一种通过减少对本地总线的访问次数来改善数据传输处理中的等待时间和吞吐量的通信设备。 总线接口1a从AALLSI4接收用户数据，并且当主机总线不能被占用时，将用户数据临时存储在数据接收缓冲器区域11中。总线接口1a中的数据接收缓冲器区域11的容量 被设置为在正常数据处理期间不满。

公开(公告)号：US06269102B1

公开(公告)日：2001-07-31

申请号：US09026395

申请日：1998-02-19

申请人： Isamu Hayashi

发明人： Isamu Hayashi

IPC分类号： G06F1328

CPC分类号： G06F13/4027

摘要： A data transfer controller (14) decides that both of a host bus (100) and a local bus (101) have been acquired by a bus interface LSI 1b by the fact that a host bus use permission GNTH from a host bus arbiter (2b) and a local bus use permission GNTL from a local bus arbiter (4) are both activated, in which case, the data transfer controller (14) controls a host bus DMA controller (12) and a local bus DMA controller (13) to make selectors SE1 and SE2 establish a connection between the host bus (100) and the local bus (101) through an inner data path (11b) having no buffer. This configuration improves data transfer rate through the host bus (100) and the local bus (101).

摘要翻译： 数据传输控制器（14）通过总线接口LSI 1b通过主机总线使用来自主机总线仲裁器（2b）的许可GNTH来确定主站总线（100）和局部总线（101） ）和来自本地总线仲裁器（4）的本地总线使用许可GNTL都被激活，在这种情况下，数据传输控制器（14）控制主机总线DMA控制器（12）和本地总线DMA控制器（13） 使选择器SE1和SE2通过没有缓冲器的内部数据路径（11b）在主机总线（100）和本地总线（101）之间建立连接。 该配置提高了通过主机总线（100）和本地总线（101）的数据传输速率。

公开(公告)号：US5347270A

公开(公告)日：1994-09-13

申请号：US889379

申请日：1992-05-28

申请人： Yoshio Matsuda ,  Harufusa Kondoh ,  Isamu Hayashi ,  Hiromi Notani

发明人： Yoshio Matsuda ,  Harufusa Kondoh ,  Isamu Hayashi ,  Hiromi Notani

IPC分类号： H01L27/10 ,  H04L12/70 ,  H04L12/931 ,  H04L12/933 ,  H04Q1/24 ,  H04Q11/04 ,  H04L12/26 ,  H04M3/26

CPC分类号： H04Q11/0421 ,  H04L49/104 ,  H04Q1/245 ,  H04Q11/0478 ,  H04L2012/5628

摘要： Incoming lines (I0 to I7) are connected to a space switch (2) through input data latches (1). The space switch (2) is connected to a normal/test changeover switch (12), which is connected to a normal/test changeover switch (13) through serial-to-parallel converting circuits (3), common buffer memories (4) and parallel-to-serial converting circuits (5). Space switches (6) are connected to the normal/test changeover switch (13). Outgoing lines (O0 to O7) are connected to the space switches 6 through output data latches (8). Connection states in the switches (2, 6) are placed in transposed relation to each other by a transposed connection generating circuit (10) in a test operation, so that the switches (2, 6) are directly connected to each other through the switches (12, 13). Predetermined data applied to the incoming lines are intactly used as expected values for judgement of the normal or abnormal operation of the set of switches of matrix structure.

摘要翻译： 输入线（I0〜I7）通过输入数据锁存器（1）连接到空间开关（2）。 空间开关（2）连接到通过串行/并行转换电路（3），公共缓冲存储器（4）连接到正常/测试转换开关（13）的正常/测试转换开关（12） 和并行到串行转换电路（5）。 空间开关（6）连接到正常/测试切换开关（13）。 输出线（O0至O7）通过输出数据锁存器（8）连接到空间开关6。 开关（2,6）中的连接状态在测试操作中通过转置连接发生电路（10）彼此置换，使得开关（2,6）通过开关彼此直接相连 （12,13）。 对输入线路应用的预定数据完全用作用于判断矩阵结构的开关组的正常或异常操作的预期值。

公开(公告)号：US08487708B2

公开(公告)日：2013-07-16

申请号：US13286208

申请日：2011-10-31

申请人： Isamu Hayashi

发明人： Isamu Hayashi

IPC分类号： H03K3/03

CPC分类号： H03L7/0996 ,  H03L2207/50

摘要： An object is to provide a method for preventing the occurrence of variations in time resolution by providing a calibration process to a TDC at the time of start up and further preventing the increase in circuit scale by reducing the redundancy of delay elements. A calibration of a multiphase oscillator TDC and a vernier TDC is carried out at the time of power-on. In the calibration, a timing input to be input to the vernier TDC is selected from output signals of DCCO based on a reference clock. Also, data is defined as an output signal which is adjacent to the output signal of DCCO mentioned above and proceeds in phase, and the delay therebetween is derived. By repeating it to all of the output signals, the one cycle of the output signal of DCCO is derived.

摘要翻译： 本发明的目的是提供一种通过在启动时向TDC提供校准处理来防止发生时间分辨率变化的方法，并且通过减少延迟元件的冗余来进一步防止电路规模的增加。 多相振荡器TDC和游标TDC的校准在上电时进行。 在校准中，基于参考时钟从DCCO的输出信号中选择输入到游标TDC的定时输入。 此外，数据被定义为与上述DCCO的输出信号相邻的输出信号，并且相位进行，并且导出它们之间的延迟。 通过重复到所有的输出信号，导出DCCO的输出信号的一个周期。