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1.发明授权Process, supply, and temperature insensitive integrated time reference circuit 有权过程，供应和温度不敏感的集成时间参考电路公开(公告)号：US07598822B2
公开(公告)日：2009-10-06
申请号：US11100783
申请日：2005-04-07
IPC分类号： H03L1/00
CPC分类号： H03K3/011 , H03K3/0231
摘要： Precision integrated time reference circuits are disclosed. Preferred embodiments provide time reference circuits that are relatively insensitive to variations in process, supply, and temperature. A preferred embodiment of the invention is disclosed in which a relaxation oscillator according to the invention includes a reference voltage circuit configured to maintain a reference voltage in proportion to actual circuit resistance values. Aspects of the invention also include dynamic compensation for variations in temperature.
摘要翻译： 公开了精密集成时间参考电路。 优选实施例提供对过程，供应和温度变化相对不敏感的时间参考电路。 公开了本发明的优选实施例，其中根据本发明的张弛振荡器包括被配置为将参考电压与实际电路电阻值成比例地保持的参考电压电路。 本发明的方面还包括温度变化的动态补偿。
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公开(公告)号：US20100060340A1
公开(公告)日：2010-03-11
申请号：US12206905
申请日：2008-09-09
IPC分类号： H03K17/28
CPC分类号： H03K17/164 , H03K17/163 , H03K17/6871 , H03K2217/0045
摘要： Various apparatuses, methods and systems for switched mode electronic circuits with reduced EMI are disclosed herein. For example, some embodiments of the present invention provide apparatuses including a power supply, an output, and a composite switch connected between the power supply and the output. The composite switch includes a plurality of transistors connected in parallel, a switch closing delay line having a plurality of switch closing outputs each connected to a control input of one of the plurality of transistors, and a switch opening delay line having a plurality of switch opening outputs each connected to one of the plurality of switch closing outputs. The switch closing delay line and switch opening delay line are connected in an order that opens the plurality of transistors in a staggered order in time and closes the plurality of transistors in a reverse staggered order in time.
摘要翻译： 本文公开了用于具有降低的EMI的开关模式电子电路的各种装置，方法和系统。 例如，本发明的一些实施例提供了包括连接在电源和输出之间的电源，输出和复合开关的装置。 复合开关包括并联连接的多个晶体管，具有多个开关闭合输出的开关闭合延迟线，每个开关闭合输出分别连接到多个晶体管之一的控制输入端，开关延迟线具有多个开关开路 每个连接到多个开关闭合输出中的一个的输出。 开关闭合延迟线和开关断开延迟线以按顺序以交错顺序打开多个晶体管的顺序连接，并且以反向交错的顺序关闭多个晶体管。
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公开(公告)号：US08115345B2
公开(公告)日：2012-02-14
申请号：US12568265
申请日：2009-09-28
IPC分类号： H03K17/00
CPC分类号： H03K17/164 , Y10T307/76 , Y10T307/826 , Y10T307/832
摘要： A low-EMI switched circuit comprises two or more switches, wherein impedance transitions of the switches are overlapped and the overlap is varied using variable switch timing based on an output power level of the switched circuit. The variable timing results in a variable impedance overlap between the switches. In one example, when one switch turns off (begins a low to high impedance transition) and a second switch turns on (begins a high to low impedance transition), a greater timing delay in beginning the second switch's transition results in a higher switch impedance overlap than a shorter delay does. If the variable timing is based on output power of the switched circuit, the variable delay can operate to reduce fly-back voltages at high power output levels and reduce shoot-through current at lower power levels, reducing EMI and quiescent current of the switched circuit.
摘要翻译： 低EMI开关电路包括两个或更多个开关，其中开关的阻抗转换重叠，并且基于开关电路的输出功率电平，使用可变开关定时改变重叠。 可变定时导致开关之间的可变阻抗重叠。 在一个示例中，当一个开关截止（从低到高阻抗转换开始）并且第二个开关导通（从高到低阻抗转换开始）时，开始第二个开关转换时更大的定时延迟导致更高的开关阻抗 重叠比较短的延迟。 如果可变定时基于开关电路的输出功率，则可变延迟可以在高功率输出电平下工作以减少反激电压并降低低功率电平的直通电流，从而降低开关电路的EMI和静态电流 。
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公开(公告)号：US20110074223A1
公开(公告)日：2011-03-31
申请号：US12568265
申请日：2009-09-28
IPC分类号： H03K17/00
CPC分类号： H03K17/164 , Y10T307/76 , Y10T307/826 , Y10T307/832
摘要： A low-EMI switched circuit comprises two or more switches, wherein impedance transitions of the switches are overlapped and the overlap is varied using variable switch timing based on an output power level of the switched circuit. The variable timing results in a variable impedance overlap between the switches. In one example, when one switch turns off (begins a low to high impedance transition) and a second switch turns on (begins a high to low impedance transition), a greater timing delay in beginning the second switch's transition results in a higher switch impedance overlap than a shorter delay does. If the variable timing is based on output power of the switched circuit, the variable delay can operate to reduce fly-back voltages at high power output levels and reduce shoot-through current at lower power levels, reducing EMI and quiescent current of the switched circuit.
摘要翻译： 低EMI开关电路包括两个或更多个开关，其中开关的阻抗转换重叠，并且基于开关电路的输出功率电平，使用可变开关定时改变重叠。 可变定时导致开关之间的可变阻抗重叠。 在一个示例中，当一个开关截止（从低到高阻抗转换开始）并且第二个开关导通（从高到低阻抗转换开始）时，开始第二个开关转换时更大的定时延迟导致更高的开关阻抗 重叠比较短的延迟。 如果可变定时基于开关电路的输出功率，则可变延迟可以在高功率输出电平下工作以减少反激电压并降低低功率电平的直通电流，从而降低开关电路的EMI和静态电流 。
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公开(公告)号：US07746123B2
公开(公告)日：2010-06-29
申请号：US12206905
申请日：2008-09-09
IPC分类号： H03K3/00
CPC分类号： H03K17/164 , H03K17/163 , H03K17/6871 , H03K2217/0045
摘要： Various apparatuses, methods and systems for switched mode electronic circuits with reduced EMI are disclosed herein. For example, some embodiments of the present invention provide apparatuses including a power supply, an output, and a composite switch connected between the power supply and the output. The composite switch includes a plurality of transistors connected in parallel, a switch closing delay line having a plurality of switch closing outputs each connected to a control input of one of the plurality of transistors, and a switch opening delay line having a plurality of switch opening outputs each connected to one of the plurality of switch closing outputs. The switch closing delay line and switch opening delay line are connected in an order that opens the plurality of transistors in a staggered order in time and closes the plurality of transistors in a reverse staggered order in time.
摘要翻译： 本文公开了用于具有降低的EMI的开关模式电子电路的各种装置，方法和系统。 例如，本发明的一些实施例提供了包括连接在电源和输出之间的电源，输出和复合开关的装置。 复合开关包括并联连接的多个晶体管，具有多个开关闭合输出的开关闭合延迟线，每个开关闭合输出分别连接到多个晶体管之一的控制输入端，开关延迟线具有多个开关开路 每个连接到多个开关闭合输出中的一个的输出。 开关闭合延迟线和开关断开延迟线以按顺序以交错顺序打开多个晶体管的顺序连接，并且以反向交错的顺序关闭多个晶体管。
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公开(公告)号：US06949984B2
公开(公告)日：2005-09-27
申请号：US10164469
申请日：2002-06-06
摘要： A voltage controlled oscillator (600) includes a voltage to current portion (400) that is inversely proportional to the semiconductor processing in order to compensate for variations both in the low-frequency and high-frequency portions of the VCO gain response. To compensate for low-frequency variations, a portion of the control current (ICTL), non-compensated control current ICTLNC (436), is subtracted from a reference current IREF (408) and the result, a low-frequency compensating control current, ICTLLF (438), is added to the non-compensated control current ICTLNC (436). To compensate for high frequency variations, a number of differential transistor pairs (410-416) are provided that have tail currents that are inversely proportional to the processing. One input (426) to all the differential pairs is connected to the VCO's control voltage while the other inputs (418-424) are connected to successively increasing voltages in the control voltage range. One output, ICTLHF (440), of all the differential pairs is summed with the non-compensated control current ICTLNC (436) while the other output of each differential pair is connected to the power supply. By adjusting the amount of non-compensated control current ICTLNC (436) provided to transistor M1 using the low frequency gain compensation circuit 402 and high frequency gain compensation circuit 404, VCO (400) provides for a process-insensitive, substantially constant gain VCO.
摘要翻译： 压控振荡器（600）包括与半导体处理成反比的电压到电流部分（400），以补偿VCO增益响应的低频部分和高频部分的变化。 为了补偿低频变化，从参考电流中减去控制电流（I CTL）的一部分，非补偿控制电流I CTLNC（436） （408），并且结果将低频补偿控制电流I CTLLF（438）加到非补偿控制电流I SUB CTLNC （436）。 为了补偿高频变化，提供了多个差分晶体管对（410-416），其具有与处理成反比的尾电流。 所有差分对的一个输入（426）连接到VCO的控制电压，而其他输入（418-424）连接到控制电压范围内的连续增加的电压。 所有差分对的一个输出I CTLH（440）与非补偿控制电流I CTLNC（436）相加，而每个差分对的另一个输出 连接到电源。 通过使用低频增益补偿电路402和高频增益补偿电路404调整提供给晶体管M 1的非补偿控制电流I CTLNC（436）的量，VCO（400）提供 过程不敏感，基本恒定的增益VCO。
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