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公开(公告)号：US20100060340A1
公开(公告)日：2010-03-11
申请号：US12206905
申请日：2008-09-09
IPC分类号： H03K17/28
CPC分类号： H03K17/164 , H03K17/163 , H03K17/6871 , H03K2217/0045
摘要： Various apparatuses, methods and systems for switched mode electronic circuits with reduced EMI are disclosed herein. For example, some embodiments of the present invention provide apparatuses including a power supply, an output, and a composite switch connected between the power supply and the output. The composite switch includes a plurality of transistors connected in parallel, a switch closing delay line having a plurality of switch closing outputs each connected to a control input of one of the plurality of transistors, and a switch opening delay line having a plurality of switch opening outputs each connected to one of the plurality of switch closing outputs. The switch closing delay line and switch opening delay line are connected in an order that opens the plurality of transistors in a staggered order in time and closes the plurality of transistors in a reverse staggered order in time.
摘要翻译： 本文公开了用于具有降低的EMI的开关模式电子电路的各种装置，方法和系统。 例如，本发明的一些实施例提供了包括连接在电源和输出之间的电源，输出和复合开关的装置。 复合开关包括并联连接的多个晶体管，具有多个开关闭合输出的开关闭合延迟线，每个开关闭合输出分别连接到多个晶体管之一的控制输入端，开关延迟线具有多个开关开路 每个连接到多个开关闭合输出中的一个的输出。 开关闭合延迟线和开关断开延迟线以按顺序以交错顺序打开多个晶体管的顺序连接，并且以反向交错的顺序关闭多个晶体管。
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公开(公告)号：US06614310B2
公开(公告)日：2003-09-02
申请号：US10001330
申请日：2001-10-31
IPC分类号： H03G320
CPC分类号： H03F1/025
摘要： The present invention provides an apparatus and method for operating driver amplifier (20) of a line driver circuit (10) from a lower set of power supply voltages, and from a higher set of voltages only when the amplitude of the signal (12) being transmitted by the line driver (20) requires it as determined by a comparator (18). Advantageously, this reduces the power dissipation in the line driver (10) by operating the line amplifier (20) the majority of the time from the lower supply voltage. A delay circuit (14) delays the signal to be amplified sufficient to allow the transitioning of the power supply voltages provided to the amplifier hysteresis of this power supply voltage switching may also be used to further reduce power dissipation.
摘要翻译： 本发明提供了一种用于仅在信号（12）的振幅为（1）的情况下才从较低的一组电源电压和较高的一组电压来操作线路驱动器电路（10）的驱动放大器（20）的装置和方法 由线路驱动器（20）传输，由比较器（18）确定。 有利地，这通过在大部分时间从较低的电源电压操作线路放大器（20）来降低线路驱动器（10）中的功率消耗。 延迟电路（14）将要放大的信号足够延迟以允许提供给该电源电压切换的放大器滞后的电源电压的转换也可用于进一步降低功耗。
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3.发明授权High efficiency wide load range buck/boost/bridge photovoltaic micro-converter 有权高效率宽负载范围降压/升压/桥式光伏微转换器公开(公告)号：US09018800B2
公开(公告)日：2015-04-28
申请号：US13194725
申请日：2011-07-29
CPC分类号： H02J1/12 , G05F1/67 , H02J3/385 , H02M3/1582 , Y02E10/58 , Y10T307/685 , Y10T307/707
摘要： Series strings of photovoltaic (PV) modules with integrated dc-dc microconverters that can function in buck, boost, or an intermediate bridge mode based on the load can harvest more energy than conventional central-inverter architectures, especially when the arrays are partially shaded or when the modules are mismatched. The integrated multi-mode dc-dc converter includes a maximum power point tracking (MPPT) algorithm that can track the true MPP, even when a PV module becomes partially-shaded, without scanning the entire output voltage range. The algorithm compares power levels only at a voltage that occurs when a bypass diode bypasses a portion of an associated PV module, and multiples thereof.
摘要翻译： 具有集成直流 - 直流微转换器的系列串联光伏（PV）模块可以在降压，升压或基于负载的中间桥接模式下工作，可以获得比传统中央 - 逆变器架构更多的能量，特别是当阵列部分阴影或 当模块不匹配时。 集成多模DC-DC转换器包括最大功率点跟踪（MPPT）算法，即使在PV模块变得部分阴影的情况下，也可以跟踪真正的MPP，而不扫描整个输出电压范围。 该算法仅在旁路二极管绕过相关联的PV模块的一部分时产生的电压及其倍数来比较功率电平。
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4.发明申请HIGH EFFICIENCY WIDE LOAD RANGE BUCK/BOOST/BRIDGE PHOTOVOLTAIC MICRO-CONVERTER 有权高效率负载范围BUCK / BOOST / BRIDGE光伏转换器公开(公告)号：US20120126624A1
公开(公告)日：2012-05-24
申请号：US13194725
申请日：2011-07-29
CPC分类号： H02J1/12 , G05F1/67 , H02J3/385 , H02M3/1582 , Y02E10/58 , Y10T307/685 , Y10T307/707
摘要： Series strings of photovoltaic (PV) modules with integrated dc-dc microconverters that can function in buck, boost, or an intermediate bridge mode based on the load can harvest more energy than conventional central-inverter architectures, especially when the arrays are partially shaded or when the modules are mismatched. The integrated multi-mode dc-dc converter includes a maximum power point tracking (MPPT) algorithm that can track the true MPP, even when a PV module becomes partially-shaded, without scanning the entire output voltage range. The algorithm compares power levels only at a voltage that occurs when a bypass diode bypasses a portion of an associated PV module, and multiples thereof.
摘要翻译： 具有集成直流 - 直流微转换器的系列串联光伏（PV）模块可以在降压，升压或基于负载的中间桥接模式下工作，可以获得比传统中央 - 逆变器架构更多的能量，特别是当阵列部分阴影或 当模块不匹配时。 集成多模DC-DC转换器包括最大功率点跟踪（MPPT）算法，即使在PV模块变得部分阴影的情况下，也可以跟踪真正的MPP，而不扫描整个输出电压范围。 该算法仅在旁路二极管绕过相关联的PV模块的一部分时产生的电压及其倍数来比较功率电平。
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公开(公告)号：US08115345B2
公开(公告)日：2012-02-14
申请号：US12568265
申请日：2009-09-28
IPC分类号： H03K17/00
CPC分类号： H03K17/164 , Y10T307/76 , Y10T307/826 , Y10T307/832
摘要： A low-EMI switched circuit comprises two or more switches, wherein impedance transitions of the switches are overlapped and the overlap is varied using variable switch timing based on an output power level of the switched circuit. The variable timing results in a variable impedance overlap between the switches. In one example, when one switch turns off (begins a low to high impedance transition) and a second switch turns on (begins a high to low impedance transition), a greater timing delay in beginning the second switch's transition results in a higher switch impedance overlap than a shorter delay does. If the variable timing is based on output power of the switched circuit, the variable delay can operate to reduce fly-back voltages at high power output levels and reduce shoot-through current at lower power levels, reducing EMI and quiescent current of the switched circuit.
摘要翻译： 低EMI开关电路包括两个或更多个开关，其中开关的阻抗转换重叠，并且基于开关电路的输出功率电平，使用可变开关定时改变重叠。 可变定时导致开关之间的可变阻抗重叠。 在一个示例中，当一个开关截止（从低到高阻抗转换开始）并且第二个开关导通（从高到低阻抗转换开始）时，开始第二个开关转换时更大的定时延迟导致更高的开关阻抗 重叠比较短的延迟。 如果可变定时基于开关电路的输出功率，则可变延迟可以在高功率输出电平下工作以减少反激电压并降低低功率电平的直通电流，从而降低开关电路的EMI和静态电流 。
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公开(公告)号：US20110012676A1
公开(公告)日：2011-01-20
申请号：US12503820
申请日：2009-07-15
IPC分类号： H03F3/217
CPC分类号： H03F3/217
摘要： Systems and methods for reduced distortion in a class D amplifier are provided. An “ideal” digital output signal is produced. The “ideal” digital output signal is then compared to the actual output signal in an error amplifier. The integrator input is the difference between the output stage waveform and the ideal output stage waveform. The net input to the integrator now comprises the imperfections of the power stage, and the feedback loop drives their average to zero. This error is then amplified and integrated. The integrated signal is than applied to a summer where it is added to the analog input. Then as in the typical Class D amplifier, the integrated signal is compared in an error amplifier to a ramp signal generated from the ramp generator.
摘要翻译： 提供了D类放大器减少失真的系统和方法。 产生“理想”数字输出信号。 然后将“理想”数字输出信号与误差放大器中的实际输出信号进行比较。 积分器输入是输出级波形与理想输出级波形之间的差异。 现在，积分器的净输入包括功率级的缺陷，反馈回路驱动其平均值为零。 然后将该误差放大并集成。 集成信号比应用于加到模拟输入的夏天。 然后如在典型的D类放大器中，积分信号在误差放大器中与从斜坡发生器产生的斜坡信号进行比较。
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7.发明授权Charge-redistribution analog-to-digital converter with reduced comparator-hysteresis effects 失效具有降低的比较器滞后效应的电荷再分配模数转换器
公开(公告)号：US5675340A
公开(公告)日：1997-10-07
申请号：US418767
申请日：1995-04-07
摘要： Methods and apparatus for an analog-to-digital converter (ADC) with reduced comparator-hysteresis effects. One embodiment uses a charge-redistribution ADC. One method performs an initial coarse analog-to-digital conversion to avoid overdriving an analog voltage comparator. One such method includes a redundant capacitor in an array of charge-redistribution capacitors used in the ADC for sample-and-hold and successive-approximation functions. Another method performs a traditional initial successive-approximation analog-to-digital conversion, and then performs an additional conversion-step test based on the least-significant bit of the initial result to correct for comparator errors in the initial conversion.
摘要翻译： 具有降低的比较器滞后效应的模数转换器（ADC）的方法和装置。 一个实施例使用电荷再分配ADC。 一种方法执行初始粗略模数转换，以避免过驱动模拟电压比较器。 一种这样的方法包括在ADC中用于采样和保持和逐次逼近功能的电荷再分配电容器阵列中的冗余电容器。 另一种方法执行传统的初始逐次逼近模数转换，然后基于初始结果的最低有效位执行额外的转换步长测试，以校正初始转换中的比较器错误。
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公开(公告)号：US07889001B2
公开(公告)日：2011-02-15
申请号：US12503820
申请日：2009-07-15
IPC分类号： H03F21/00
CPC分类号： H03F3/217
摘要： Systems and methods for reduced distortion in a class D amplifier are provided. An “ideal” digital output signal is produced. The “ideal” digital output signal is then compared to the actual output signal in an error amplifier. The integrator input is the difference between the output stage waveform and the ideal output stage waveform. The net input to the integrator now comprises the imperfections of the power stage, and the feedback loop drives their average to zero. This error is then amplified and integrated. The integrated signal is than applied to a summer where it is added to the analog input. Then as in the typical Class D amplifier, the integrated signal is compared in an error amplifier to a ramp signal generated from the ramp generator.
摘要翻译： 提供了D类放大器减少失真的系统和方法。 产生“理想”数字输出信号。 然后将“理想”数字输出信号与误差放大器中的实际输出信号进行比较。 积分器输入是输出级波形与理想输出级波形之间的差异。 现在，积分器的净输入包括功率级的缺陷，反馈回路驱动其平均值为零。 然后将该误差放大并集成。 集成信号比应用于加到模拟输入的夏天。 然后如在典型的D类放大器中，积分信号在误差放大器中与从斜坡发生器产生的斜坡信号进行比较。
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公开(公告)号：US20110074223A1
公开(公告)日：2011-03-31
申请号：US12568265
申请日：2009-09-28
IPC分类号： H03K17/00
CPC分类号： H03K17/164 , Y10T307/76 , Y10T307/826 , Y10T307/832
摘要： A low-EMI switched circuit comprises two or more switches, wherein impedance transitions of the switches are overlapped and the overlap is varied using variable switch timing based on an output power level of the switched circuit. The variable timing results in a variable impedance overlap between the switches. In one example, when one switch turns off (begins a low to high impedance transition) and a second switch turns on (begins a high to low impedance transition), a greater timing delay in beginning the second switch's transition results in a higher switch impedance overlap than a shorter delay does. If the variable timing is based on output power of the switched circuit, the variable delay can operate to reduce fly-back voltages at high power output levels and reduce shoot-through current at lower power levels, reducing EMI and quiescent current of the switched circuit.
摘要翻译： 低EMI开关电路包括两个或更多个开关，其中开关的阻抗转换重叠，并且基于开关电路的输出功率电平，使用可变开关定时改变重叠。 可变定时导致开关之间的可变阻抗重叠。 在一个示例中，当一个开关截止（从低到高阻抗转换开始）并且第二个开关导通（从高到低阻抗转换开始）时，开始第二个开关转换时更大的定时延迟导致更高的开关阻抗 重叠比较短的延迟。 如果可变定时基于开关电路的输出功率，则可变延迟可以在高功率输出电平下工作以减少反激电压并降低低功率电平的直通电流，从而降低开关电路的EMI和静态电流 。
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公开(公告)号：US07746123B2
公开(公告)日：2010-06-29
申请号：US12206905
申请日：2008-09-09
IPC分类号： H03K3/00
CPC分类号： H03K17/164 , H03K17/163 , H03K17/6871 , H03K2217/0045
摘要： Various apparatuses, methods and systems for switched mode electronic circuits with reduced EMI are disclosed herein. For example, some embodiments of the present invention provide apparatuses including a power supply, an output, and a composite switch connected between the power supply and the output. The composite switch includes a plurality of transistors connected in parallel, a switch closing delay line having a plurality of switch closing outputs each connected to a control input of one of the plurality of transistors, and a switch opening delay line having a plurality of switch opening outputs each connected to one of the plurality of switch closing outputs. The switch closing delay line and switch opening delay line are connected in an order that opens the plurality of transistors in a staggered order in time and closes the plurality of transistors in a reverse staggered order in time.
摘要翻译： 本文公开了用于具有降低的EMI的开关模式电子电路的各种装置，方法和系统。 例如，本发明的一些实施例提供了包括连接在电源和输出之间的电源，输出和复合开关的装置。 复合开关包括并联连接的多个晶体管，具有多个开关闭合输出的开关闭合延迟线，每个开关闭合输出分别连接到多个晶体管之一的控制输入端，开关延迟线具有多个开关开路 每个连接到多个开关闭合输出中的一个的输出。 开关闭合延迟线和开关断开延迟线以按顺序以交错顺序打开多个晶体管的顺序连接，并且以反向交错的顺序关闭多个晶体管。
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