公开(公告)号：US07328296B1

公开(公告)日：2008-02-05

申请号：US11324695

申请日：2006-01-03

申请人： Naser Marmash ,  Avinash Kallat ,  Brandon L. Paul ,  Mark Botello ,  Andrew Kniager

发明人： Naser Marmash ,  Avinash Kallat ,  Brandon L. Paul ,  Mark Botello ,  Andrew Kniager

IPC分类号： G06F13/24

CPC分类号： G06F13/24

摘要： An interrupt processing system having an interrupt holding registers, each corresponding to a different class of interrupts. A write queue posts servicing required by the interrupt holding registers. An interrupt vector register has bit positions corresponding to different classes of interrupts. A read queue has inputs coupled to the plurality of interrupt holding registers and to the interrupt vector register. Detection logic is coupled between an arbiter, fed by the write and read queues, and a processor for: (a) indicating when an interrupt has passed from the write arbiter to the processor; (b) detecting the interrupt class of such passed interrupt; (c) enabling the one of the bit positions corresponding to the detected interrupt class in the interrupt vector register to store a state indicating the servicing requirement for such detected class of interrupt; and (d) wherein the data stored in the interrupt vector register is passed to the processor through the read queue and the arbiter selector.

摘要翻译： 一种具有中断保持寄存器的中断处理系统，每个中断处理系统对应于不同类别的中断。 写入队列中断保存寄存器所需的服务。 中断向量寄存器具有对应于不同类别中断的位位置。 读取队列具有耦合到多个中断保持寄存器和中断向量寄存器的输入。 检测逻辑耦合在由写入和读取队列馈送的仲裁器之间，以及处理器，用于：（a）指示中断何时从写入仲裁器传递到处理器; （b）检测这种传递中断的中断类; （c）使能与中断向量寄存器中检测到的中断类别相对应的位位置之一存储指示这种检测到的中断类别的服务要求的状态; 和（d）其中存储在中断向量寄存器中的数据通过读队列和仲裁器选择器传递给处理器。

公开(公告)号：US07398343B1

公开(公告)日：2008-07-08

申请号：US11324667

申请日：2006-01-03

申请人： Naser Marmash ,  Avinash Kallat ,  Brandon L. Paul ,  Mark Botello ,  Andrew Kniager

发明人： Naser Marmash ,  Avinash Kallat ,  Brandon L. Paul ,  Mark Botello ,  Andrew Kniager

IPC分类号： G06F13/24

CPC分类号： G06F13/24

摘要： An interrupt processing system having an interrupt holding registers, each corresponding to a different class of interrupts. A write queue posts servicing required by the interrupt holding registers. An interrupt vector register has bit positions corresponding to different classes of interrupts. A read queue has inputs coupled to the plurality of interrupt holding registers and to the interrupt vector register. Detection logic is coupled between an arbiter, fed by the write and read queues, and a processor for: (a) indicating when an interrupt has passed from the write arbiter to the processor; (b) detecting the interrupt class of such passed interrupt; (c) enabling the one of the bit positions corresponding to the detected interrupt class in the interrupt vector register to store a state indicating the servicing requirement for such detected class of interrupt; and (d) wherein the data stored in the interrupt vector register is passed to the processor through the read queue and the arbiter selector.

公开(公告)号：US07325084B1

公开(公告)日：2008-01-29

申请号：US11324666

申请日：2006-01-03

申请人： Naser Marmash ,  Avinash Kallat ,  Brandon L. Paul ,  Mark Botello ,  Andrew Kniager

发明人： Naser Marmash ,  Avinash Kallat ,  Brandon L. Paul ,  Mark Botello ,  Andrew Kniager

IPC分类号： G06F13/24

CPC分类号： G06F13/24

摘要： An interrupt processing system having an interrupt holding registers, each corresponding to a different class of interrupts. A write queue posts servicing required by the interrupt holding registers. An interrupt vector register has bit positions corresponding to different classes of interrupts. A read queue has inputs coupled to the plurality of interrupt holding registers and to the interrupt vector register. Detection logic is coupled between an arbiter, fed by the write and read queues, and a processor for: (a) indicating when an interrupt has passed from the write arbiter to the processor; (b) detecting the interrupt class of such passed interrupt; (c) enabling the one of the bit positions corresponding to the detected interrupt class in the interrupt vector register to store a state indicating the servicing requirement for such detected class of interrupt; and (d) wherein the data stored in the interrupt vector register is passed to the processor through the read queue and the arbiter selector.

摘要翻译： 一种具有中断保持寄存器的中断处理系统，每个中断处理系统对应于不同类别的中断。 写入队列中断保存寄存器所需的服务。 中断向量寄存器具有对应于不同类别中断的位位置。 读取队列具有耦合到多个中断保持寄存器和中断向量寄存器的输入。 检测逻辑耦合在由写入和读取队列馈送的仲裁器之间，以及处理器，用于：（a）指示中断何时从写入仲裁器传递到处理器; （b）检测这种传递中断的中断类; （c）使能与中断向量寄存器中检测到的中断类别相对应的位位置之一存储指示这种检测到的中断类别的服务要求的状态; 和（d）其中存储在中断向量寄存器中的数据通过读队列和仲裁器选择器传递给处理器。