公开(公告)号：US07178120B2

公开(公告)日：2007-02-13

申请号：US10338929

申请日：2003-01-08

申请人： Nathaniel Hieter ,  David J. Hathaway ,  Prabhakar Kudva ,  David S. Kung ,  Leon Stok

发明人： Nathaniel Hieter ,  David J. Hathaway ,  Prabhakar Kudva ,  David S. Kung ,  Leon Stok

IPC分类号： G06H17/50 ,  G06H9/45

CPC分类号： G06F17/505 ,  G06F17/5072

摘要： A method for performing timing closure on VLSI chips in a distributed environment is described. Abstracting the physical and timing resources of a chip and providing an asynchronous method of updating that abstraction allows multiple partitions of a chip to be optimized concurrently. A global view of physical and timing resources is supplied to local optimizations which are applied concurrently to achieve timing closure. Portions of the hierarchy are optimized in separate processes. Partitioning of the chip is performed along hierarchical lines, with each process owning a single partition in the hierarchy. The processes may be executed by a single computer, or spread across multiple computers in a local network. While optimizations performed by a single process are only applied to its given portion of the hierarchy, decisions are made in the context of the entire hierarchy. These optimizations include placement, synthesis, and routing. The present method can also be expanded to include other resources, such as routing resource, power supply current, power/thermal budget, substrate noise budget, and the like, all of which being able to be similarly abstracted and shared.

摘要翻译： 描述了在分布式环境中对VLSI芯片执行定时闭合的方法。 提取芯片的物理和定时资源并提供更新抽象的异步方法，可以同时优化芯片的多个分区。 将物理和时序资源的全局视图提供给同时实现时序收敛的局部优化。 层次结构的部分在单独的进程中进行了优化。 芯片的分区按照层次线执行，每个进程在层次结构中拥有单个分区。 这些过程可以由单个计算机执行，或者分布在本地网络中的多个计算机上。 虽然单个进程执行的优化仅适用于其给定的层次结构部分，但是在整个层次结构的上下文中进行决策。 这些优化包括放置，合成和路由。 本方法还可以扩展到包括路由资源，电源电流，功率/热预算，衬底噪声预算等其他资源，所有这些资源都能被类似地抽象和共享。

公开(公告)号：US20070192752A1

公开(公告)日：2007-08-16

申请号：US11354425

申请日：2006-02-15

申请人： Subhrajit Bhattacharya ,  Anthony Correale ,  Nathaniel Hieter ,  Veena Pureswaran ,  Ruchir Puri

发明人： Subhrajit Bhattacharya ,  Anthony Correale ,  Nathaniel Hieter ,  Veena Pureswaran ,  Ruchir Puri

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F2217/08

摘要： An improved solution for designing a circuit is provided. A set of target paths, each of which has a performance attribute that is targeted for improvement, is obtained from a design for the circuit. An influence for one or more of the nodes in the set of target paths is obtained. One or more of the nodes are selected for improvement using the influence. Subsequently, the performance attribute for each selected node is improved. For example, an implementation of the node can be replaced with an implementation having an improved performance attribute. The relative improvement provided by an alternative implementation versus a relative detriment to another performance attribute can be obtained and used in selecting the node(s) for improvement. In one embodiment, the relative improvement and influence are used to obtain a sensitivity metric for each alternative implementation, which is used in selecting the node(s) for improvement. In this manner, the circuit can be improved in a more effective manner.

摘要翻译： 提供了一种改进的设计电路解决方案。 从电路的设计中获得一组目标路径，每个目标路径具有旨在改进的性能属性。 获得对目标路径集中的一个或多个节点的影响。 选择一个或多个节点用于使用影响进行改进。 随后，提高了每个选定节点的性能属性。 例如，可以用具有改进的性能属性的实现来替换节点的实现。 可以获得替代实现提供的相对改进与对另一性能属性的相对损害，并用于选择节点以进行改进。 在一个实施例中，使用相对改进和影响来获得用于选择节点以进行改进的每个备选实现的灵敏度度量。 以这种方式，可以以更有效的方式改善电路。