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12 条记录 (耗时 0.024 秒)

    Method for performing timing closure on VLSI chips in a distributed environment
    1.
    发明授权
    Method for performing timing closure on VLSI chips in a distributed environment 失效
    在分布式环境中对VLSI芯片进行定时关闭的方法

    公开(公告)号：US07178120B2

    公开(公告)日：2007-02-13

    申请号：US10338929

    申请日：2003-01-08

    申请人： Nathaniel Hieter ,  David J. Hathaway ,  Prabhakar Kudva ,  David S. Kung ,  Leon Stok

    发明人： Nathaniel Hieter ,  David J. Hathaway ,  Prabhakar Kudva ,  David S. Kung ,  Leon Stok

    IPC分类号： G06H17/50 ,  G06H9/45

    CPC分类号： G06F17/505 ,  G06F17/5072

    摘要： A method for performing timing closure on VLSI chips in a distributed environment is described. Abstracting the physical and timing resources of a chip and providing an asynchronous method of updating that abstraction allows multiple partitions of a chip to be optimized concurrently. A global view of physical and timing resources is supplied to local optimizations which are applied concurrently to achieve timing closure. Portions of the hierarchy are optimized in separate processes. Partitioning of the chip is performed along hierarchical lines, with each process owning a single partition in the hierarchy. The processes may be executed by a single computer, or spread across multiple computers in a local network. While optimizations performed by a single process are only applied to its given portion of the hierarchy, decisions are made in the context of the entire hierarchy. These optimizations include placement, synthesis, and routing. The present method can also be expanded to include other resources, such as routing resource, power supply current, power/thermal budget, substrate noise budget, and the like, all of which being able to be similarly abstracted and shared.

    摘要翻译： 描述了在分布式环境中对VLSI芯片执行定时闭合的方法。 提取芯片的物理和定时资源并提供更新抽象的异步方法，可以同时优化芯片的多个分区。 将物理和时序资源的全局视图提供给同时实现时序收敛的局部优化。 层次结构的部分在单独的进程中进行了优化。 芯片的分区按照层次线执行，每个进程在层次结构中拥有单个分区。 这些过程可以由单个计算机执行，或者分布在本地网络中的多个计算机上。 虽然单个进程执行的优化仅适用于其给定的层次结构部分，但是在整个层次结构的上下文中进行决策。 这些优化包括放置，合成和路由。 本方法还可以扩展到包括路由资源，电源电流，功率/热预算，衬底噪声预算等其他资源，所有这些资源都能被类似地抽象和共享。

    Method and apparatus for logic synthesis employing size independent timing optimization
    2.
    发明授权
    Method and apparatus for logic synthesis employing size independent timing optimization 失效
    用于逻辑合成的方法和装置，采用大小独立的时序优化

    公开(公告)号：US6167557A

    公开(公告)日：2000-12-26

    申请号：US67336

    申请日：1998-04-28

    申请人： Prabhakarn N. Kudva ,  David S. Kung ,  Leon Stok

    发明人： Prabhakarn N. Kudva ,  David S. Kung ,  Leon Stok

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505

    摘要： Size independent timing optimization is performed on an initial circuit design using gain based models for logic cell types. A component library containing various logic elements in a plurality of sizes is provided and a single gain based model for each logic element (cell type) is created therefrom. Initial conditions for gain and delay are then established for each cell type. Gain based optimization, which is size independent, is then performed on the initial circuit design. The optimized size independent solution is then transformed into a realizable discrete circuit solution.

    摘要翻译： 在使用基于逻辑单元类型的增益模型的初始电路设计上执行尺寸独立的时序优化。 提供了包含多种尺寸的各种逻辑元件的组件库，并且从其中创建了用于每个逻辑元件（单元格类型）的单个基于增益的模型。 然后为每种细胞类型建立增益和延迟的初始条件。 然后在初始电路设计中执行与尺寸无关的基于增益的优化。 然后将优化的尺寸独立解决方案转换为可实现的分立电路解决方案。

    CMOS tapered gate and synthesis method
    6.
    发明授权
    CMOS tapered gate and synthesis method 失效
    CMOS锥形栅极及其合成方法

    公开(公告)号：US06966046B2

    公开(公告)日：2005-11-15

    申请号：US09841505

    申请日：2001-04-24

    申请人： Brian W. Curran ,  Lisa Bryant Lacey ,  Gregory A. Northrop ,  Ruchir Puri ,  Leon Stok

    发明人： Brian W. Curran ,  Lisa Bryant Lacey ,  Gregory A. Northrop ,  Ruchir Puri ,  Leon Stok

    IPC分类号： G06F17/50 ,  H01L21/82 ,  H03K19/096 ,  H03K19/20

    CPC分类号： G06F17/505

    摘要： A high-performance gate library is augmented with tapered gates. The widths of the stacked devices are varied to reduce the delay through some of the input pins. For example in a tapered NAND gate the bottom devices in the NFET stack are have longer widths than the top device to achieve smaller top input to output pin delay at the expense of larger bottom input to output pin delay. The method of using synthesis algorithms modifies the input net to gate pin connections and swaps traditional non-tapered gates with tapered gates to improve the delay of the timing critical paths. The latest arriving gate input net is swapped with the net connected to the top pin. The gate is then converted to a tapered gate provided the paths through the bottom gate input(s) that are not timing critical.

    摘要翻译： 高性能门库增加了锥形门。 改变堆叠器件的宽度以减少通过一些输入引脚的延迟。 例如在锥形NAND门中，NFET堆叠中的底部器件具有比顶部器件更宽的宽度，以牺牲较大的底部输入到输出引脚延迟为代价来实现较小的顶部输入以输出引脚延迟。 使用合成算法的方法将输入网络修改为栅极引脚连接，并与锥形栅极交换传统的非锥形栅极，以改善时序关键路径的延迟。 最新到达的门输入网络被互换，网络连接到顶针。 然后将栅极转换成锥形栅极，提供通过底栅输入（不是时序关键）的路径。

    Method for preserving regularity during logic synthesis
    8.
    发明授权
    Method for preserving regularity during logic synthesis 失效
    在逻辑合成期间保持规律性的方法

    公开(公告)号：US06557159B1

    公开(公告)日：2003-04-29

    申请号：US09578090

    申请日：2000-05-24

    申请人： Thomas Kutzschebauch ,  Leon Stok

    发明人： Thomas Kutzschebauch ,  Leon Stok

    IPC分类号： G06F1750

    CPC分类号： G06F17/505

    摘要： The present invention concerns a method for maintaining regularity in a netlist during logic synthesis. The method determines a global regularity for the netlist. The method determines a group of elements in the netlist having similar regularity signatures. Further, the method applies a transform to the group of elements.

    摘要翻译： 本发明涉及一种在逻辑综合期间维持网表规则性的方法。 该方法确定网表的全局规律性。 该方法确定具有相似规则性签名的网表中的一组元素。 此外，该方法将变换应用于该组元素。

    Wavefront technology mapping
    9.
    发明授权
    Wavefront technology mapping 失效
    波前技术映射

    公开(公告)号：US06334205B1

    公开(公告)日：2001-12-25

    申请号：US09255538

    申请日：1999-02-22

    申请人： Mahesh A. Iyer ,  Leon Stok ,  Andrew J. Sullivan

    发明人： Mahesh A. Iyer ,  Leon Stok ,  Andrew J. Sullivan

    IPC分类号： G06F1750

    CPC分类号： G06F17/505

    摘要： A technology mapping method and device for mapping cost functions on directed acyclic graphs, using decoupled matching and covering and circumventing the memory explosion usually caused by this decoupling. Multiple matches are generated at the head of a wavefront process and embedded within the network. Covering is done at the tail of the wavefront to optimize one or more cost functions.

    摘要翻译： 一种技术映射方法和设备，用于映射有向非循环图上的成本函数，使用去耦匹配并覆盖和规避通常由该解耦造成的内存爆炸。 在波前处理的头部生成多个匹配并嵌入到网络中。 覆盖在波前的尾部完成，以优化一个或多个成本函数。