公开(公告)号：US08339862B2

公开(公告)日：2012-12-25

申请号：US12343552

申请日：2008-12-24

申请人： Natsuo Aiika ,  Shoii Shukuri ,  Satoshi Shimizu ,  Taku Ogura

发明人： Natsuo Aiika ,  Shoii Shukuri ,  Satoshi Shimizu ,  Taku Ogura

IPC分类号： G11C16/06 ,  G11C11/34 ,  H01L29/792

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/12 ,  H01L27/115 ,  H01L27/11524

摘要： According to an aspect of the present invention, it is provided: a nonvolatile semiconductor memory device comprising: a plurality of bit lines arranged in a first direction; a plurality of source lines arranged in the first direction, the plurality of source lines being parallel to the plurality of bit lines, the plurality of source lines being distinct from the plurality of bit lines; a plurality of memory gate lines arranged in a second direction perpendicular to the first direction; a plurality of memory cells arranged in a matrix, each of the plurality of memory cells including a p type MIS nonvolatile transistor having a first terminal, a second terminal, a channel between the first terminal and the second terminal, a gate insulation film formed on the channel, a gate electrode connected to one corresponding memory gate line of the plurality of memory gate lines, and a carrier storage layer formed between the gate insulation film and the gate electrode, the first terminal being connected to one corresponding bit line of the plurality of bit lines and the second terminal being connected to one corresponding source line of the plurality of source lines.

摘要翻译： 根据本发明的一个方面，提供一种非易失性半导体存储器件，包括：沿第一方向布置的多个位线; 沿所述第一方向布置的多条源极线，所述多条源极线与所述多个位线平行，所述多个源极线与所述多个位线不同; 沿垂直于第一方向的第二方向布置的多个存储栅极线; 多个存储单元，以矩阵形式布置，所述多个存储单元中的每一个包括具有第一端子，第二端子，第一端子和第二端子之间的通道的ap型MIS非易失性晶体管，形成在栅极绝缘膜上的栅极绝缘膜 连接到所述多个存储栅极线中的一个对应的存储栅极线的栅极，以及形成在所述栅极绝缘膜和所述栅电极之间的载流子存储层，所述第一端子连接到所述多个栅极线中的一个相应的位线 位线，并且所述第二端子连接到所述多个源极线中的一个对应的源极线。

公开(公告)号：US20090161439A1

公开(公告)日：2009-06-25

申请号：US12343552

申请日：2008-12-24

申请人： Natsuo Aiika ,  Shoii Shukuri ,  Satoshi Shimizu ,  Taku Ogura

发明人： Natsuo Aiika ,  Shoii Shukuri ,  Satoshi Shimizu ,  Taku Ogura

IPC分类号： G11C16/06 ,  G11C11/34 ,  H01L29/792

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/12 ,  H01L27/115 ,  H01L27/11524

摘要： According to an aspect of the present invention, it is provided: a nonvolatile semiconductor memory device comprising: a plurality of bit lines arranged in a first direction; a plurality of source lines arranged in the first direction, the plurality of source lines being parallel to the plurality of bit lines, the plurality of source lines being distinct from the plurality of bit lines; a plurality of memory gate lines arranged in a second direction perpendicular to the first direction; a plurality of memory cells arranged in a matrix, each of the plurality of memory cells including a p type MIS nonvolatile transistor having a first terminal, a second terminal, a channel between the first terminal and the second terminal, a gate insulation film formed on the channel, a gate electrode connected to one corresponding memory gate line of the plurality of memory gate lines, and a carrier storage layer formed between the gate insulation film and the gate electrode, the first terminal being connected to one corresponding bit line of the plurality of bit lines and the second terminal being connected to one corresponding source line of the plurality of source lines.

摘要翻译： 根据本发明的一个方面，提供一种非易失性半导体存储器件，包括：沿第一方向布置的多个位线; 沿所述第一方向布置的多条源极线，所述多条源极线与所述多个位线平行，所述多个源极线与所述多个位线不同; 沿垂直于第一方向的第二方向布置的多个存储栅极线; 多个存储单元，以矩阵形式布置，所述多个存储单元中的每一个包括具有第一端子，第二端子，第一端子和第二端子之间的通道的ap型MIS非易失性晶体管，形成在栅极绝缘膜上的栅极绝缘膜 连接到所述多个存储栅极线中的一个对应的存储栅极线的栅极，以及形成在所述栅极绝缘膜和所述栅电极之间的载流子存储层，所述第一端子连接到所述多个栅极线中的一个相应的位线 位线，并且所述第二端子连接到所述多个源极线中的一个对应的源极线。