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公开(公告)号：US20050180376A1
公开(公告)日：2005-08-18
申请号：US11035508
申请日：2005-01-14
CPC分类号： H04L27/2626 , H04B7/2621 , H04L5/023 , H04L27/2607
摘要： A system and method is provided for processing four samples per clock period of an orthogonal frequency division multiplex symbol 10 having a length not a multiple of four. The method includes providing a sequence of data samples 12 and a sequence of non-data samples 14 and 16. The method includes selecting four input samples from one of the data samples 12 and the non-data samples 14 and 16 based on a clock signal. The method includes storing at least a portion of contents of a first group of memory cells 112 in a second group of memory cells 116. The first group of memory cells 112 comprised of four memory cells 112a-d. The method also provides for storing the selected four input samples in the first group of memory cells 112.
摘要翻译： 提供了一种用于处理具有不超过四倍的长度的正交频分复用符号10的每个时钟周期的四个采样的系统和方法。 该方法包括提供数据样本序列12和非数据样本14和16的序列。该方法包括基于时钟信号从数据样本12和非数据样本14和16中的一个中选择四个输入样本 。 该方法包括将第一组存储器单元112的内容的至少一部分存储在第二组存储器单元116中。 第一组存储器单元112由四个存储器单元112a-d组成。 该方法还提供将所选择的四个输入样本存储在第一组存储器单元112中。
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公开(公告)号：US07304977B2
公开(公告)日：2007-12-04
申请号：US11035508
申请日：2005-01-14
CPC分类号： H04L27/2626 , H04B7/2621 , H04L5/023 , H04L27/2607
摘要： A sequence of data samples and a sequence of non-data samples are provided. Four input samples from one of the data samples and the non-data samples are selected based on a clock signal. At least a portion of contents of a first group of memory cells are stored in a second group of memory cells. The first group of memory cells are comprised of four memory cells. The selected four input samples are stored in the first group of memory cells.
摘要翻译： 提供了一系列数据样本和非数据样本序列。 基于时钟信号选择来自数据样本和非数据样本之一的四个输入样本。 第一组存储器单元的内容的至少一部分被存储在第二组存储器单元中。 第一组存储单元由四个存储单元组成。 所选择的四个输入样本存储在第一组存储单元中。
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公开(公告)号：US20060224651A1
公开(公告)日：2006-10-05
申请号：US11095275
申请日：2005-03-31
申请人： Srinadh Madhavapeddi , Manish Goel , Henry Angulo
发明人： Srinadh Madhavapeddi , Manish Goel , Henry Angulo
IPC分类号： G06F17/14
CPC分类号： G06F17/142
摘要： A system (12) for determining discrete transforms as between time and frequency domains. The system comprises a grid (60) comprising adders and multipliers. The grid is operable to perform in parallel an integer number P operations of a first transform function selected from one of either an IFFT or an FFT. The system also comprises the integer number of P serially-operating pipelines (641-648). Each of the pipelines is coupled to the grid and is operable to perform serially over a number of cycles an integer number S operations of the first transform. In the system, S and P are both greater than one and, in combination, the grid and the serially-operating pipelines perform the first transform type as an S×P-point transform. In a first instance at least a portion of the grid is operable to perform IFFT operations. In a second instance at least a portion of the grid is operable to perform FFT operations.
摘要翻译： 一种用于确定时域和频域之间的离散变换的系统（12）。 该系统包括包括加法器和乘法器的格（60）。 网格可操作以并行执行从IFFT或FFT中的一个中选择的第一变换函数的整数P运算。 该系统还包括整数个P串行操作的管线（64×1〜64＆lt; 8＆gt;）。 每个管道耦合到电网并且可操作以串行地执行第一变换的整数S个操作的多个周期。 在系统中，S和P都大于1，并且组合在一起，网格和串行操作的管线执行第一变换类型作为SxP点变换。 在第一情况下，网格的至少一部分可操作以执行IFFT操作。 在第二种情况下，网格的至少一部分可操作以执行FFT操作。
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公开(公告)号：US20110084771A1
公开(公告)日：2011-04-14
申请号：US12577168
申请日：2009-10-10
IPC分类号： H03B5/18
CPC分类号： H03B5/1228 , H03B5/1212 , H03B5/1215 , H03B5/1243
摘要： Various apparatuses and methods for a low phase noise frequency synthesizer are disclosed herein. For example, some embodiments provide an oscillator that may be used in a low phase noise frequency synthesizer. The oscillator includes a tank circuit, a plurality of cross-coupled transistor pairs connected to the tank circuit, a current source connected to the plurality of cross-coupled transistor pairs, and at least one switch connected to the plurality of cross-coupled transistor pairs. The switch is adapted to activate a subset of the plurality of cross-coupled transistor pairs and to deactivate another subset of the plurality of cross-coupled transistor pairs to operate the tank circuit in the oscillator using the activated subset of the plurality of cross-coupled transistor pairs.
摘要翻译： 本文公开了用于低相位噪声频率合成器的各种装置和方法。 例如，一些实施例提供了可用于低相位噪声频率合成器中的振荡器。 该振荡器包括一个振荡电路，一个连接到该振荡电路的多个交叉耦合晶体管对，一个连接到多个交叉耦合晶体管对的电流源，以及至少一个连接到多个交叉耦合晶体管对的开关 。 开关适于激活多个交叉耦合晶体管对的子集，并且使多个交叉耦合晶体管对的另一子集失效，以使用多个交叉耦合晶体管对的激活子集来操作振荡器中的振荡电路 晶体管对。
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公开(公告)号：US07877536B2
公开(公告)日：2011-01-25
申请号：US11964609
申请日：2007-12-26
CPC分类号： G06F13/4221
摘要： A Peripheral Component Interconnect (PCI) Express switch is provided. The PCI Express switch includes a first routing information bus connected to the first port; a second routing information bus connected to the second port; a third routing information bus connected to the third port; two routing slaves in the first port, each dedicated to listening to one of the second and the third routing information buses; two routing slaves in the second port, each dedicated to listening to one of the first and the third routing information buses; and two routing slaves in the third port, each dedicated to listening to one of the first and the second routing information buses.
摘要翻译： 提供外设部件互连（PCI）Express交换机。 PCI Express交换机包括连接到第一端口的第一路由信息总线; 连接到第二端口的第二路由信息总线; 连接到第三端口的第三路由信息总线; 第一端口中的两个路由从站，每个专用于监听第二和第三路由信息总线中的一个; 第二端口中的两个路由从站，每个专用于监听第一和第三路由信息总线之一; 以及第三端口中的两个路由从站，每个专用于监听第一和第二路由信息总线之一。
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公开(公告)号：US20090172237A1
公开(公告)日：2009-07-02
申请号：US11964609
申请日：2007-12-26
IPC分类号： G06F13/14
CPC分类号： G06F13/4221
摘要： A Peripheral Component Interconnect (PCI) Express switch is provided. The PCI Express switch includes a first routing information bus connected to the first port; a second routing information bus connected to the second port; a third routing information bus connected to the third port; two routing slaves in the first port, each dedicated to listening to one of the second and the third routing information buses; two routing slaves in the second port, each dedicated to listening to one of the first and the third routing information buses; and two routing slaves in the third port, each dedicated to listening to one of the first and the second routing information buses.
摘要翻译： 提供外设组件互连（PCI）Express交换机。 PCI Express交换机包括连接到第一端口的第一路由信息总线; 连接到第二端口的第二路由信息总线; 连接到第三端口的第三路由信息总线; 第一端口中的两个路由从站，每个专用于监听第二和第三路由信息总线中的一个; 第二端口中的两个路由从站，每个专用于监听第一和第三路由信息总线之一; 以及第三端口中的两个路由从站，每个专用于监听第一和第二路由信息总线之一。
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公开(公告)号：US08022778B2
公开(公告)日：2011-09-20
申请号：US12577168
申请日：2009-10-10
IPC分类号： H03B5/12
CPC分类号： H03B5/1228 , H03B5/1212 , H03B5/1215 , H03B5/1243
摘要： Various apparatuses and methods for a low phase noise frequency synthesizer are disclosed herein. For example, some embodiments provide an oscillator that may be used in a low phase noise frequency synthesizer. The oscillator includes a tank circuit, a plurality of cross-coupled transistor pairs connected to the tank circuit, a current source connected to the plurality of cross-coupled transistor pairs, and at least one switch connected to the plurality of cross-coupled transistor pairs. The switch is adapted to activate a subset of the plurality of cross-coupled transistor pairs and to deactivate another subset of the plurality of cross-coupled transistor pairs to operate the tank circuit in the oscillator using the activated subset of the plurality of cross-coupled transistor pairs.
摘要翻译： 本文公开了用于低相位噪声频率合成器的各种装置和方法。 例如，一些实施例提供了可用于低相位噪声频率合成器中的振荡器。 该振荡器包括一个振荡电路，一个连接到该振荡电路的多个交叉耦合晶体管对，一个连接到多个交叉耦合晶体管对的电流源，以及至少一个连接到多个交叉耦合晶体管对的开关 。 开关适于激活多个交叉耦合晶体管对的子集，并且使多个交叉耦合晶体管对的另一子集失效，以使用多个交叉耦合晶体管对的激活子集来操作振荡器中的振荡电路 晶体管对。
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