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公开(公告)号：US08330159B2
公开(公告)日：2012-12-11
申请号：US11933841
申请日：2007-11-01
申请人： Jeffrey Lee Large , Henry Litzmann Edwards , Ayman A. Fayed , Patrick Cruise , Kah Mun Low , Neeraj Nayak , Oguz Altun , Chris Barr
发明人： Jeffrey Lee Large , Henry Litzmann Edwards , Ayman A. Fayed , Patrick Cruise , Kah Mun Low , Neeraj Nayak , Oguz Altun , Chris Barr
CPC分类号： H01L23/58 , H01L22/22 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit (IC) includes a substrate having a device layer and a plurality of metal layers formed thereon. The plurality of metal layers include patterned upper metal layers and lower metal layers, a multi-level metal interconnect structure formed using the plurality of metal layers, where the interconnect structure is in electrical contact with a first portion and second portion of the device layer. At least one circuit editing structure including a first and second columns are formed using at least a portion of the plurality of metal layers, the first column being in electrical contact with the first portion of the device layer and the second column being in electrical contact with second portion of the device layer, where a portion of the first and second columns define a circuit editing feature operable to electrically couple or decouple the columns using focused ion beam (FIB) processing.
摘要翻译： 集成电路（IC）包括具有器件层和形成在其上的多个金属层的衬底。 多个金属层包括图案化的上金属层和下金属层，使用多个金属层形成的多层金属互连结构，其中互连结构与器件层的第一部分和第二部分电接触。 使用多个金属层的至少一部分形成包括第一和第二列的至少一个电路编辑结构，第一列与器件层的第一部分电接触，第二列与第二列电接触 器件层的第二部分，其中第一和第二列的一部分限定电路编辑特征，其可操作以使用聚焦离子束（FIB）处理电耦合或解耦列。
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公开(公告)号：US20100119011A1
公开(公告)日：2010-05-13
申请号：US12617124
申请日：2009-11-12
CPC分类号： H03K5/1565 , H03L7/18
摘要： A device is provided for dividing a clock signal by even and odd integers. The device includes a divider, a delay portion and a duty cycle corrector. The divider is arranged to receive the clock signal and can divide the clock signal and output a divided clock signal. The delay portion can output a delayed signal based on the divided clock signal. The duty cycle corrector can output a first signal based on the delayed signal and the divided clock signal.
摘要翻译： 提供了一种用于将时钟信号除以偶数和奇数整数的装置。 该装置包括分频器，延迟部分和占空比校正器。 分频器被布置成接收时钟信号，并且可以分频时钟信号并输出分频时钟信号。 延迟部分可以基于划分的时钟信号输出延迟的信号。 占空比校正器可以基于延迟信号和分频时钟信号输出第一信号。
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公开(公告)号：US20090114912A1
公开(公告)日：2009-05-07
申请号：US11933841
申请日：2007-11-01
申请人： Jeffrey Lee Large , Henry Litzmann Edwards , Ayman A. Fayed , Patrick Cruise , Kah Mun Low , Neeraj Nayak , Oguz Altun , Chris Barr
发明人： Jeffrey Lee Large , Henry Litzmann Edwards , Ayman A. Fayed , Patrick Cruise , Kah Mun Low , Neeraj Nayak , Oguz Altun , Chris Barr
CPC分类号： H01L23/58 , H01L22/22 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit (IC) includes a substrate having a device layer and a plurality of metal layers formed thereon. The plurality of metal layers include patterned upper metal layers and lower metal layers, a multi-level metal interconnect structure formed using the plurality of metal layers, where the interconnect structure is in electrical contact with a first portion and second portion of the device layer. At least one circuit editing structure including a first and second columns are formed using at least a portion of the plurality of metal layers, the first column being in electrical contact with the first portion of the device layer and the second column being in electrical contact with second portion of the device layer, where a portion of the first and second columns define a circuit editing feature operable to electrically couple or decouple the columns using focused ion beam (FIB) processing.
摘要翻译： 集成电路（IC）包括具有器件层和形成在其上的多个金属层的衬底。 多个金属层包括图案化的上金属层和下金属层，使用多个金属层形成的多层金属互连结构，其中互连结构与器件层的第一部分和第二部分电接触。 使用多个金属层的至少一部分形成包括第一和第二列的至少一个电路编辑结构，第一列与器件层的第一部分电接触，第二列与第二列电接触 器件层的第二部分，其中第一和第二列的一部分限定电路编辑特征，其可操作以使用聚焦离子束（FIB）处理来电耦合或解耦列。
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公开(公告)号：US20110053537A1
公开(公告)日：2011-03-03
申请号：US12550437
申请日：2009-08-31
IPC分类号： H04B1/16
CPC分类号： H04B1/1027 , H04W52/0245 , Y02D70/40
摘要： A frequency modulation (FM) receiver with a low power frequency synthesizer. A FM receiver includes a low noise amplifier for processing a received input signal, a frequency synthesizer having an oscillator for generating a local oscillator signal by supplying a bias current to the oscillator, and a mixer for generating an intermediate frequency signal by mixing the received input signal with the local oscillator signal. The FM receiver further includes an analog to digital converter for converting the intermediate frequency signal to a digital signal and a bias current control module for measuring a signal strength of the received input signal based on the digital signal and for controlling the bias current.
摘要翻译： 具有低功率频率合成器的调频（FM）接收机。 FM接收机包括用于处理接收到的输入信号的低噪声放大器，具有用于通过向振荡器提供偏置电流来产生本地振荡器信号的振荡器的频率合成器，以及用于通过混合接收的输入来产生中频信号的混频器 信号与本地振荡器信号。 FM接收器还包括用于将中频信号转换为数字信号的模/数转换器和用于基于数字信号测量接收的输入信号的信号强度并用于控制偏置电流的偏置电流控制模块。
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公开(公告)号：US20100225367A1
公开(公告)日：2010-09-09
申请号：US12707682
申请日：2010-02-18
申请人： Sriram Murali , Karthik Suburaj , Neeraj Nayak
发明人： Sriram Murali , Karthik Suburaj , Neeraj Nayak
IPC分类号： H03L7/085
摘要： Frequency synthesizer with immunity from oscillator pulling. The frequency synthesizer for generating an output frequency includes an oscillator that is capable of generating a first frequency. The frequency synthesizer also includes an output divider coupled to the oscillator. The output divider is configurable to allow the oscillator to generate a second frequency to prevent degradation in phase noise due to an interference to the first frequency of the oscillator, and to generate the output frequency from the second frequency.
摘要翻译： 具有振荡器拉动抗扰度的频率合成器。 用于产生输出频率的频率合成器包括能够产生第一频率的振荡器。 频率合成器还包括耦合到振荡器的输出分频器。 输出分频器可配置为允许振荡器产生第二频率，以防止由于对振荡器的第一频率的干扰导致的相位噪声的劣化，并且从第二频率产生输出频率。
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公开(公告)号：US08344774B2
公开(公告)日：2013-01-01
申请号：US12707682
申请日：2010-02-18
申请人： Sriram Murali , Karthik Subburaj , Neeraj Nayak
发明人： Sriram Murali , Karthik Subburaj , Neeraj Nayak
IPC分类号： H03L7/06
摘要： Frequency synthesizer with immunity from oscillator pulling. The frequency synthesizer for generating an output frequency includes an oscillator that is capable of generating a first frequency. The frequency synthesizer also includes an output divider coupled to the oscillator. The output divider is configurable to allow the oscillator to generate a second frequency to prevent degradation in phase noise due to an interference to the first frequency of the oscillator, and to generate the output frequency from the second frequency.
摘要翻译： 具有振荡器拉动抗扰度的频率合成器。 用于产生输出频率的频率合成器包括能够产生第一频率的振荡器。 频率合成器还包括耦合到振荡器的输出分频器。 输出分频器可配置为允许振荡器产生第二频率，以防止由于对振荡器的第一频率的干扰导致的相位噪声的劣化，并且从第二频率产生输出频率。
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公开(公告)号：US08280331B2
公开(公告)日：2012-10-02
申请号：US12617124
申请日：2009-11-12
IPC分类号： H04B1/06
CPC分类号： H03K5/1565 , H03L7/18
摘要： A device is provided for dividing a clock signal by even and odd integers. The device includes a divider, a delay portion and a duty cycle corrector. The divider is arranged to receive the clock signal and can divide the clock signal and output a divided clock signal. The delay portion can output a delayed signal based on the divided clock signal. The duty cycle corrector can output a first signal based on the delayed signal and the divided clock signal.
摘要翻译： 提供了一种用于将时钟信号除以偶数和奇数整数的装置。 该装置包括分频器，延迟部分和占空比校正器。 分频器被布置成接收时钟信号，并且可以分频时钟信号并输出分频时钟信号。 延迟部分可以基于划分的时钟信号输出延迟的信号。 占空比校正器可以基于延迟信号和分频时钟信号输出第一信号。
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公开(公告)号：US20110084771A1
公开(公告)日：2011-04-14
申请号：US12577168
申请日：2009-10-10
IPC分类号： H03B5/18
CPC分类号： H03B5/1228 , H03B5/1212 , H03B5/1215 , H03B5/1243
摘要： Various apparatuses and methods for a low phase noise frequency synthesizer are disclosed herein. For example, some embodiments provide an oscillator that may be used in a low phase noise frequency synthesizer. The oscillator includes a tank circuit, a plurality of cross-coupled transistor pairs connected to the tank circuit, a current source connected to the plurality of cross-coupled transistor pairs, and at least one switch connected to the plurality of cross-coupled transistor pairs. The switch is adapted to activate a subset of the plurality of cross-coupled transistor pairs and to deactivate another subset of the plurality of cross-coupled transistor pairs to operate the tank circuit in the oscillator using the activated subset of the plurality of cross-coupled transistor pairs.
摘要翻译： 本文公开了用于低相位噪声频率合成器的各种装置和方法。 例如，一些实施例提供了可用于低相位噪声频率合成器中的振荡器。 该振荡器包括一个振荡电路，一个连接到该振荡电路的多个交叉耦合晶体管对，一个连接到多个交叉耦合晶体管对的电流源，以及至少一个连接到多个交叉耦合晶体管对的开关 。 开关适于激活多个交叉耦合晶体管对的子集，并且使多个交叉耦合晶体管对的另一子集失效，以使用多个交叉耦合晶体管对的激活子集来操作振荡器中的振荡电路 晶体管对。
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公开(公告)号：US08022778B2
公开(公告)日：2011-09-20
申请号：US12577168
申请日：2009-10-10
IPC分类号： H03B5/12
CPC分类号： H03B5/1228 , H03B5/1212 , H03B5/1215 , H03B5/1243
摘要： Various apparatuses and methods for a low phase noise frequency synthesizer are disclosed herein. For example, some embodiments provide an oscillator that may be used in a low phase noise frequency synthesizer. The oscillator includes a tank circuit, a plurality of cross-coupled transistor pairs connected to the tank circuit, a current source connected to the plurality of cross-coupled transistor pairs, and at least one switch connected to the plurality of cross-coupled transistor pairs. The switch is adapted to activate a subset of the plurality of cross-coupled transistor pairs and to deactivate another subset of the plurality of cross-coupled transistor pairs to operate the tank circuit in the oscillator using the activated subset of the plurality of cross-coupled transistor pairs.
摘要翻译： 本文公开了用于低相位噪声频率合成器的各种装置和方法。 例如，一些实施例提供了可用于低相位噪声频率合成器中的振荡器。 该振荡器包括一个振荡电路，一个连接到该振荡电路的多个交叉耦合晶体管对，一个连接到多个交叉耦合晶体管对的电流源，以及至少一个连接到多个交叉耦合晶体管对的开关 。 开关适于激活多个交叉耦合晶体管对的子集，并且使多个交叉耦合晶体管对的另一子集失效，以使用多个交叉耦合晶体管对的激活子集来操作振荡器中的振荡电路 晶体管对。
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