公开(公告)号：US20060265868A1

公开(公告)日：2006-11-30

申请号：US11487027

申请日：2006-07-14

Applicant: Neal Rueger ,  Chris Hill ,  Zailong Bian ,  John Smythe

Inventor： Neal Rueger ,  Chris Hill ,  Zailong Bian ,  John Smythe

IPC: H01R43/00

CPC classification number: H01L21/76837 ,  H01L21/76834 ,  H01L23/53223 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10T29/49117 ,  H01L2924/00

Abstract: An inter-metal dielectric (IMD) fill process includes depositing an insulating nanolaminate barrier layer. The nanolaminate is preferably an oxide liner formed by using an alternating layer deposition process. The layer is highly conformal and is an excellent diffusion barrier. Gaps between metal lines are filled using high density plasma chemical vapor deposition with a reactive species gas. The barrier layer protects the metal lines from shorts between neighboring layers. The resulting structure has substantially uneroded metal lines and an insulating IMD fill.

公开(公告)号：US20060038293A1

公开(公告)日：2006-02-23

申请号：US10924707

申请日：2004-08-23

Applicant: Neal Rueger ,  Chris Hill ,  Zailong Bian ,  John Smythe

Inventor： Neal Rueger ,  Chris Hill ,  Zailong Bian ,  John Smythe

IPC: H01L23/52 ,  H01L23/48

CPC classification number: H01L21/76837 ,  H01L21/76834 ,  H01L23/53223 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10T29/49117 ,  H01L2924/00

Abstract: An inter-metal dielectric (IMD) fill process includes depositing an insulating nanolaminate barrier layer. The nanolaminate is preferably an oxide liner formed by using an alternating layer deposition process. The layer is highly conformal and is an excellent diffusion barrier. Gaps between metal lines are filled using high density plasma chemical vapor deposition with a reactive species gas. The barrier layer protects the metal lines from shorts between neighboring layers. The resulting structure has substantially uneroded metal lines and an insulating IMD fill.

Abstract translation: 金属间电介质（IMD）填充工艺包括沉积绝缘的纳米层间隔离层。 纳米酸盐优选是通过使用交替层沉积工艺形成的氧化物衬垫。 该层是高度保形的，是一个很好的扩散屏障。 使用具有反应性物质气体的高密度等离子体化学气相沉积来填充金属线之间的间隙。 阻挡层保护金属线免受相邻层之间的短路。 所得到的结构具有基本上未编码的金属线和绝缘IMD填充物。

公开(公告)号：US20060246719A1

公开(公告)日：2006-11-02

申请号：US11457723

申请日：2006-07-14

Applicant: Neal Rueger ,  Chris Hill ,  Zailong Bian ,  John Smythe

Inventor： Neal Rueger ,  Chris Hill ,  Zailong Bian ,  John Smythe

IPC: H01L21/4763

CPC classification number: H01L21/76837 ,  H01L21/76834 ,  H01L23/53223 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10T29/49117 ,  H01L2924/00

Abstract: An inter-metal dielectric (IMD) fill process includes depositing an insulating nanolaminate barrier layer. The nanolaminate is preferably an oxide liner formed by using an alternating layer deposition process. The layer is highly conformal and is an excellent diffusion barrier. Gaps between metal lines are filled using high density plasma chemical vapor deposition with a reactive species gas. The barrier layer protects the metal lines from shorts between neighboring layers. The resulting structure has substantially uneroded metal lines and an insulating IMD fill.

Abstract translation: 金属间电介质（IMD）填充工艺包括沉积绝缘的纳米层间隔离层。 纳米酸盐优选是通过使用交替层沉积工艺形成的氧化物衬垫。 该层是高度保形的，是一个很好的扩散屏障。 使用具有反应性物质气体的高密度等离子体化学气相沉积来填充金属线之间的间隙。 阻挡层保护金属线免受相邻层之间的短路。 所得到的结构具有基本上未编码的金属线和绝缘IMD填充物。

公开(公告)号：US07439157B2

公开(公告)日：2008-10-21

申请号：US11129884

申请日：2005-05-16

Applicant: Zailong Bian ,  John Smythe ,  Janos Fucsko ,  Michael Violette

Inventor： Zailong Bian ,  John Smythe ,  Janos Fucsko ,  Michael Violette

IPC: H01L21/76

CPC classification number: H01L21/76232 ,  H01L27/11517

Abstract: A method includes removing a portion of a substrate to define an isolation trench; forming a first dielectric layer on exposed surfaces of the substrate in the trench; forming a second dielectric layer on at least the first dielectric layer, the second dielectric layer containing a different dielectric material than the first dielectric layer; depositing a third dielectric layer to fill the trench; removing an upper portion of the third dielectric layer from the trench and leaving a lower portion covering a portion of the second dielectric layer; oxidizing the lower portion of the third dielectric layer after removing the upper portion; removing an exposed portion of the second dielectric layer from the trench, thereby exposing a portion of the first dielectric layer; and forming a fourth dielectric layer in the trench covering the exposed portion of the first dielectric layer.

Abstract translation: 一种方法包括去除衬底的一部分以限定隔离沟槽; 在所述沟槽中的所述衬底的暴露表面上形成第一电介质层; 在至少所述第一介电层上形成第二电介质层，所述第二电介质层含有与所述第一电介质层不同的电介质材料; 沉积第三介电层以填充沟槽; 从沟槽移除第三电介质层的上部并留下覆盖第二介电层的一部分的下部; 在除去上部之后氧化第三电介质层的下部; 从所述沟槽去除所述第二电介质层的暴露部分，从而暴露所述第一介电层的一部分; 以及在所述沟槽中形成覆盖所述第一介电层的暴露部分的第四电介质层。

公开(公告)号：US20050287731A1

公开(公告)日：2005-12-29

申请号：US11129884

申请日：2005-05-16

Applicant: Zailong Bian ,  John Smythe ,  Janos Fucsko ,  Michael Violette

Inventor： Zailong Bian ,  John Smythe ,  Janos Fucsko ,  Michael Violette

IPC: H01L21/762 ,  H01L21/8238 ,  H01L21/8247 ,  H01L29/788

CPC classification number: H01L21/76232 ,  H01L27/11517

Abstract: A method includes removing a portion of a substrate to define an isolation trench; forming a first dielectric layer on exposed surfaces of the substrate in the trench; forming a second dielectric layer on at least the first dielectric layer, the second dielectric layer containing a different dielectric material than the first dielectric layer; depositing a third dielectric layer to fill the trench; removing an upper portion of the third dielectric layer from the trench and leaving a lower portion covering a portion of the second dielectric layer; oxidizing the lower portion of the third dielectric layer after removing the upper portion; removing an exposed portion of the second dielectric layer from the trench, thereby exposing a portion of the first dielectric layer; and forming a fourth dielectric layer in the trench covering the exposed portion of the first dielectric layer.

Abstract translation: 一种方法包括去除衬底的一部分以限定隔离沟槽; 在所述沟槽中的所述衬底的暴露表面上形成第一电介质层; 在至少所述第一介电层上形成第二电介质层，所述第二电介质层含有与所述第一电介质层不同的电介质材料; 沉积第三介电层以填充沟槽; 从沟槽移除第三电介质层的上部并留下覆盖第二介电层的一部分的下部; 在除去上部之后氧化第三电介质层的下部; 从所述沟槽去除所述第二电介质层的暴露部分，从而暴露所述第一介电层的一部分; 以及在所述沟槽中形成覆盖所述第一介电层的暴露部分的第四电介质层。

公开(公告)号：US08597974B2

公开(公告)日：2013-12-03

申请号：US12843640

申请日：2010-07-26

Applicant: Zailong Bian

Inventor： Zailong Bian

IPC: H01L21/00

CPC classification number: H01L45/1253 ,  H01C1/02 ,  H01C7/13 ,  H01C17/06 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1683 ,  Y10T29/49099

Abstract: Methods, devices, and systems associated with resistance variable memory device structures are described herein. In one or more embodiments, a method of forming a confined resistance variable memory cell structure includes forming a resistance variable material such that a first unmodified portion of the resistance variable material contacts a bottom electrode and a second unmodified portion of the resistance variable material contacts a top electrode.

Abstract translation: 本文描述了与电阻可变存储器件结构相关联的方法，器件和系统。 在一个或多个实施例中，形成限制电阻可变存储单元结构的方法包括形成电阻可变材料，使得电阻可变材料的第一未修改部分接触底电极，并且电阻可变材料的第二未修改部分接触 顶部电极。

公开(公告)号：US07968425B2

公开(公告)日：2011-06-28

申请号：US11486691

申请日：2006-07-14

Applicant: Zailong Bian ,  Xiaolong Fang

Inventor： Zailong Bian ,  Xiaolong Fang

IPC: H01L21/76 ,  H01L21/3105 ,  H01L21/469

CPC classification number: H01L21/76232 ,  H01L27/115 ,  H01L27/11521

Abstract: Methods and apparatus are provided. An isolation region is formed by lining a trench formed in a substrate with a first dielectric layer by forming the first dielectric layer adjoining exposed substrate surfaces within the trench using a high-density plasma process, forming a layer of spin-on dielectric material on the first dielectric layer so as to fill a remaining portion of the trench, and densifying the layer of spin-on dielectric material.

Abstract translation: 提供了方法和装置。 通过使用高密度等离子体工艺形成与沟槽内暴露的衬底表面邻接的第一介电层，在第一介电层上形成一层旋涂电介质材料，形成隔离区 第一电介质层，以便填充沟槽的剩余部分，并且使自旋电介质材料层致密化。

公开(公告)号：US20100276780A1

公开(公告)日：2010-11-04

申请号：US12835042

申请日：2010-07-13

Applicant: Zailong Bian ,  Janos Fucsko

Inventor： Zailong Bian ,  Janos Fucsko

IPC: H01L29/06

CPC classification number: H01L29/0649 ,  H01L21/762 ,  H01L21/764 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/0642 ,  H01L29/0653 ,  H01L29/78

Abstract: The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.

Abstract translation: 本发明包括具有沟槽隔离区域的半导体结构。 沟槽隔离区域的沟槽可以包括底部的窄底部部分和上部宽部分。 电绝缘材料可以填充上部宽部分，同时留下狭窄底部内的空隙。 沟槽隔离区域可以并入存储器阵列中，和/或可并入到电子系统中。 本发明还包括形成半导体结构的方法。

公开(公告)号：US08546888B2

公开(公告)日：2013-10-01

申请号：US13164085

申请日：2011-06-20

Applicant: Zailong Bian ,  Xiaolong Fang

Inventor： Zailong Bian ,  Xiaolong Fang

IPC: H01L21/70

CPC classification number: H01L21/76232 ,  H01L27/115 ,  H01L27/11521

Abstract: Methods and apparatus are provided. An isolation region is formed by lining a trench formed in a substrate with a first dielectric layer by forming the first dielectric layer adjoining exposed substrate surfaces within the trench using a high-density plasma process, forming a layer of spin-on dielectric material on the first dielectric layer so as to fill a remaining portion of the trench, and densifying the layer of spin-on dielectric material.

Abstract translation: 提供了方法和装置。 通过使用高密度等离子体工艺形成与沟槽内暴露的衬底表面邻接的第一介电层，在第一介电层上形成一层旋涂电介质材料，形成隔离区 第一电介质层，以便填充沟槽的剩余部分，并且使自旋电介质材料层致密化。

公开(公告)号：US07772672B2

公开(公告)日：2010-08-10

申请号：US11218231

申请日：2005-09-01

Applicant: Zailong Bian ,  Janos Fucsko

Inventor： Zailong Bian ,  Janos Fucsko

IPC: H01L29/00

CPC classification number: H01L29/0649 ,  H01L21/762 ,  H01L21/764 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/0642 ,  H01L29/0653 ,  H01L29/78

Abstract: The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.

Abstract translation: 本发明包括具有沟槽隔离区域的半导体结构。 沟槽隔离区域的沟槽可以包括底部的窄底部部分和上部宽部分。 电绝缘材料可以填充上部宽部分，同时留下狭窄底部内的空隙。 沟槽隔离区域可以并入存储器阵列中，和/或可并入到电子系统中。 本发明还包括形成半导体结构的方法。