公开(公告)号：US06742057B2

公开(公告)日：2004-05-25

申请号：US09870917

申请日：2001-05-31

申请人： Neal T. Wingen ,  Eric Lai ,  Arnaud Moser ,  Ronald De Vries ,  Ramaswamy Subramanian

发明人： Neal T. Wingen ,  Eric Lai ,  Arnaud Moser ,  Ronald De Vries ,  Ramaswamy Subramanian

IPC分类号： G06F1314

CPC分类号： G06F13/385

摘要： A configurable universal asynchronous receiver/transmitter (UART) facilitates efforts to upgrade UART functionality in the field and replace older UART devices. In one example embodiment, an integrated circuit includes a universal asynchronous receiver/transmitter configured and arranged to operate in one of a plurality of modes, with each mode being selectable in response to mode-selecting data. The integrated circuit device includes an interface circuit electrically connected to the universal asynchronous receiver/transmitter and adapted to present the mode-selecting data to the universal asynchronous receiver/transmitter. The integrated circuit device also includes a selection circuit adapted to enable the mode-selecting data to pass from the interface circuit to the universal asynchronous receiver/transmitter.

摘要翻译： 可配置的通用异步收发器（UART）有助于在现场升级UART功能，并替代旧的UART设备。 在一个示例实施例中，集成电路包括配置和布置为以多种模式之一操作的通用异步接收器/发射器，每种模式可响应于模式选择数据而选择。 集成电路装置包括电连接到通用异步接收器/发射器并且适于将模式选择数据呈现给通用异步接收器/发射器的接口电路。 集成电路装置还包括适于使模式选择数据从接口电路传递到通用异步接收器/发送器的选择电路。

公开(公告)号：US5608734A

公开(公告)日：1997-03-04

申请号：US560738

申请日：1995-11-20

申请人： Lorin H. Sandler ,  Neal T. Wingen

发明人： Lorin H. Sandler ,  Neal T. Wingen

IPC分类号： H04J3/06 ,  H04L7/08

CPC分类号： H04J3/0608

摘要： A method and apparatus for framing data in digital transmission lines automatically recognizes a framing format. The apparatus preferably includes a frame alignment apparatus that can recognize any one of a number of predetermined framing formats created by framing information on an input signal. The frame alignment apparatus outputs an aligning signal to an output frame counter, which counts the data and framing information on the input signal and outputs a frame synchronization signal according to the framing format. The input signal is also coupled to an output apparatus that outputs the input signal at the clock rate of a terminating apparatus. The frame alignment apparatus preferably includes a plurality of pattern recognizers able to recognize at least one of the framing formats and a storage apparatus for storing counts of successive data and framing information that match a framing pattern. The counts are preferably used to identify the framing information on the input signal and the framing format.

摘要翻译： 用于在数字传输线中成帧数据的方法和装置自动识别成帧格式。 该装置优选地包括帧对准装置，其能够识别通过对输入信号进行成帧信息而产生的多个预定成帧格式中的任何一个。 帧对准装置将对准信号输出到输出帧计数器，该计数器对输入信号的数据和成帧信息进行计数，并根据成帧格式输出帧同步信号。 输入信号还耦合到以端接装置的时钟速率输出输入信号的输出装置。 帧对准装置优选地包括能够识别至少一个成帧格式的多个模式识别器和用于存储与成帧模式匹配的连续数据和成帧信息的计数的存储装置。 该计数优选地用于识别关于输入信号和成帧格式的成帧信息。

公开(公告)号：US5557614A

公开(公告)日：1996-09-17

申请号：US172458

申请日：1993-12-22

申请人： Lorin H. Sandler ,  Neal T. Wingen

发明人： Lorin H. Sandler ,  Neal T. Wingen

IPC分类号： H04J3/06

CPC分类号： H04J3/0608

摘要： A method and apparatus for framing data in digital transmission lines automatically recognizes a framing format. The apparatus preferably includes a frame alignment apparatus that can recognize any one of a number of predetermined framing formats created by framing information on an input signal. The frame alignment apparatus outputs an aligning signal to an output frame counter, which counts the data and framing information on the input signal and outputs a frame synchronization signal according to the framing format. The input signal is also coupled to an output apparatus that outputs the input signal at the clock rate of a terminating apparatus. The frame alignment apparatus preferably includes a plurality of pattern recognizers able to recognize at least one of the framing formats and a storage apparatus for storing counts of successive data and framing information that match a framing pattern. The counts are preferably used to identify the flaming information on the input signal and the flaming format.

摘要翻译： 用于在数字传输线中成帧数据的方法和装置自动识别成帧格式。 该装置优选地包括帧对准装置，其能够识别通过对输入信号进行成帧信息而产生的多个预定成帧格式中的任何一个。 帧对准装置将对准信号输出到输出帧计数器，该计数器对输入信号的数据和成帧信息进行计数，并根据成帧格式输出帧同步信号。 输入信号还耦合到以端接装置的时钟速率输出输入信号的输出装置。 帧对准装置优选地包括能够识别至少一个成帧格式的多个模式识别器和用于存储与成帧模式匹配的连续数据和成帧信息的计数的存储装置。 这些计数优选地用于识别关于输入信号和燃烧格式的燃烧信息。

公开(公告)号：US06621293B2

公开(公告)日：2003-09-16

申请号：US09871231

申请日：2001-05-31

申请人： Neal T. Wingen

发明人： Neal T. Wingen

IPC分类号： G06F738

CPC分类号： G06F13/385

摘要： An integrated circuit arrangement is reconfigurable in the field to operate in one of a plurality of modes, including a test mode, in response to mode-selecting codes presented via a temporary register in the circuit. In one example embodiment, an arrangement of integrated circuits includes a reconfigurable integrated circuit configured and arranged to operate in one of a plurality of modes. The reconfigurable integrated circuit includes a register adapted to store data for temporary use, with each operating mode of the reconfigurable circuit being selectable in response to mode-selecting data code. An interface circuit is electrically connected to the reconfigurable integrated circuit and is adapted to present the mode-selecting data code to the reconfigurable integrated circuit. A selection circuit is adapted to enable the interface circuit to pass mode-selecting data to the reconfigurable integrated circuit. The selection circuit is also adapted to detect when a series of data writes to the register corresponds to the mode-selecting data code and, in response, to reconfigure the integrated circuit to operate in one of the plurality of modes.

公开(公告)号：US06820145B2

公开(公告)日：2004-11-16

申请号：US09871027

申请日：2001-05-31

申请人： Neal T. Wingen

发明人： Neal T. Wingen

IPC分类号： G06F1314

CPC分类号： G06F13/385

摘要： A circuit arrangement improves CPU efficiency by processing data through a FIFO circuit of a UART chip using a CPU adapted to detect, and respond with various options to, the current storage capacity of the FIFO circuit. In one example embodiment, a circuit arrangement includes a universal asynchronous receiver/transmitter (UART) chip having a FIFO circuit and an arithmetic logic unit (ALU) adapted to generate an N-bit variable binary signal, wherein the binary signal varies as a function of a current storage capacity of the FIFO circuit. The circuit arrangement further includes a control circuit communicatively coupled with the UART chip that is adapted to read the N-bit variable binary signal and, in response, to control the data flow through the FIFO circuit.

摘要翻译： 电路装置通过使用CPU的UART电路的FIFO电路处理数据来提高CPU效率，该CPU适用于检测FIFO电路的当前存储容量并对其进行各种选择。 在一个示例实施例中，电路装置包括具有FIFO电路和适于产生N位可变二进制信号的算术逻辑单元（ALU）的通用异步接收器/发射器（UART）芯片，其中二进制信号作为一个功能变化 的当前存储容量的FIFO电路。 电路装置还包括与UART芯片通信耦合的控制电路，该控制电路适于读取N位可变二进制信号，并且响应于控制通过FIFO电路的数据流。

公开(公告)号：US09910454B2

公开(公告)日：2018-03-06

申请号：US13490729

申请日：2012-06-07

申请人： William John Bainbridge ,  Stephen W. Hamilton ,  Neal T. Wingen

发明人： William John Bainbridge ,  Stephen W. Hamilton ,  Neal T. Wingen

IPC分类号： H04L7/00 ,  G06F1/12 ,  H04J3/06

CPC分类号： G06F1/12 ,  H04J3/0697

摘要： Data payload is passed over a boundary from a sender module (SM) on one side of the boundary to a receiver module (RM) on the other side of the boundary. The SM has two or more multiplexers to pass the data payload over to a receiver storage register in the RM. Each multiplexer has 1) its own read address pointer lane coming from sequencing logic located on the RM side and 2) data slots to send data payload from that multiplexer across the boundary to the receiver storage register in the RM in a qualified event synchronization. The sequencing logic ensures that the multiple read address pointers going to the multiplexers have a fixed alternating relationship amongst themselves; and thus, the multiple read address pointers syncopate between each other to move the data payload across the boundary to provide 100% throughput.

公开(公告)号：US20130329842A1

公开(公告)日：2013-12-12

申请号：US13490729

申请日：2012-06-07

申请人： William John Bainbridge ,  Stephen W. Hamilton ,  Neal T. Wingen

发明人： William John Bainbridge ,  Stephen W. Hamilton ,  Neal T. Wingen

IPC分类号： H04L7/00

CPC分类号： G06F1/12 ,  H04J3/0697

摘要： Data payload is passed over a boundary from a sender module (SM) on one side of the boundary to a receiver module (RM) on the other side of the boundary. The SM has two or more multiplexers to pass the data payload over to a receiver storage register in the RM. Each multiplexer has 1) its own read address pointer lane coming from sequencing logic located on the RM side and 2) data slots to send data payload from that multiplexer across the boundary to the receiver storage register in the RM in a qualified event synchronization. The sequencing logic ensures that the multiple read address pointers going to the multiplexers have a fixed alternating relationship amongst themselves; and thus, the multiple read address pointers syncopate between each other to move the data payload across the boundary to provide 100% throughput.

摘要翻译： 数据有效载荷从边界一侧的发送器模块（SM）到边界另一侧的接收器模块（RM）通过边界传递。 SM具有两个或多个多路复用器，以将数据有效载荷传递到RM中的接收器存储寄存器。 每个复用器具有1）来自位于RM侧的排序逻辑的自己的读地址指针通道，以及2）数据时隙，以在合格事件同步中将数据有效载荷从跨越边界的多路复用器发送到RM中的接收器存储寄存器。 排序逻辑确保去往多路复用器的多个读地址指针在它们之间具有固定的交替关系; 并且因此，多个读取地址指针彼此之间相互重合以跨越边界移动数据有效载荷以提供100％的吞吐量。

公开(公告)号：US06895518B2

公开(公告)日：2005-05-17

申请号：US09870918

申请日：2001-05-31

申请人： Neal T. Wingen

发明人： Neal T. Wingen

IPC分类号： G06F1/04 ,  G06F13/38 ,  G06F13/42 ,  H04L7/04 ,  H04L25/38 ,  G06F1/32

CPC分类号： G06F13/385 ,  Y02D10/14 ,  Y02D10/151

摘要： The present invention embodiment comprises an arrangement of integrated circuits with a UART device that is configurable to operate in a power-reduced mode while the clock frequency of serial data communication remains constant. In one example embodiment, an arrangement of a plurality of integrated circuit devices includes a first integrated circuit device driven by a first clock signal at a first clock rate. The arrangement contains a parallel data bus coupled to communicate with the first integrated circuit device in response to the first clock signal. The arrangement also includes a universal asynchronous receiver/transmitter (UART) chip with a serial communication circuit adapted to communicate serial data at a second rate defined by a second clock signal. The UART chip also encompasses a parallel bus interface circuit responsive to the first clock signal and adapted to pass data between the parallel data bus and the serial communication circuit. The UART chip also houses a data-storage-register circuit adapted to output status data to the parallel data bus, the status data being indicative of states of at least one of the serial communication circuit and the parallel bus interface circuit. The arrangement of integrated circuit devices further includes a clock control circuit adapted to reduce the first clock rate in response to a clock control signal. By reducing the first clock rate, the UART chip is configured to operate in a power-reduced mode while the serial communication circuit concurrently communicates serial data at the second rate.

摘要翻译： 本发明实施例包括具有UART装置的集成电路的布置，其可配置为在串行数据通信的时钟频率保持恒定的同时以功率降低模式工作。 在一个示例实施例中，多个集成电路器件的布置包括以第一时钟速率由第一时钟信号驱动的第一集成电路器件。 该装置包含耦合以响应于第一时钟信号与第一集成电路装置通信的并行数据总线。 该装置还包括具有串行通信电路的通用异步收发器（UART）芯片，该串行通信电路适于以由第二时钟信号定义的第二速率传送串行数据。 UART芯片还包括响应于第一时钟信号并且适于在并行数据总线和串行通信电路之间传递数据的并行总线接口电路。 UART芯片还容纳适于将状态数据输出到并行数据总线的数据存储寄存器电路，状态数据指示串行通信电路和并行总线接口电路中的至少一个的状态。 集成电路装置的布置还包括时钟控制电路，其适于响应于时钟控制信号而减小第一时钟速率。 通过降低第一时钟速率，UART芯片被配置为在功率降低模式下工作，而串行通信电路以第二速率同时传送串行数据。