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1.发明申请Method and Apparatus for Modifying a Virtual Processor Model for Hardware/Software Simulation 有权用于修改硬件/软件仿真的虚拟处理器模型的方法和装置公开(公告)号：US20080319730A1
公开(公告)日：2008-12-25
申请号：US12159831
申请日：2007-07-30
IPC分类号： G06F15/00
CPC分类号： G06F17/5022 , G06F17/5009 , G06F2217/86
摘要： A method of transforming a provided virtual processor model to a user virtual processor model. Also a tool, e.g., provided as instructions for operating in a host computer system for converting a provided virtual processor model to a user virtual processor model. Also a method of specifying one or more characteristics of a target processor to transform a provided virtual processor model to a user virtual processor model that when operating in a c-simulation system, simulates the operation of the target processor. For example, a method of specifying one or more characteristics of instructions to transform a provided virtual processor model to a user virtual processor model.
摘要翻译： 将所提供的虚拟处理器模型变换为用户虚拟处理器模型的方法。 还提供了一种工具，例如作为用于在主计算机系统中操作以用于将所提供的虚拟处理器模型转换为用户虚拟处理器模型的指令来提供的工具。 还有一种指定目标处理器的一个或多个特征的方法，以将提供的虚拟处理器模型转换成在c仿真系统中操作时模拟目标处理器的操作的用户虚拟处理器模型。 例如，指定将所提供的虚拟处理器模型转换成用户虚拟处理器模型的指令的一个或多个特性的方法。
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公开(公告)号：US07567893B2
公开(公告)日：2009-07-28
申请号：US11315683
申请日：2005-12-20
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A simulation system, a computer product to implement a simulation method, and a method of simulating a digital circuit that has at least one element and at least one clock signal having clock attributes. The method includes maintaining a data structure for time-scheduled events scheduled to occur at particular simulation-times; and maintaining a data structure for clock-scheduled events each corresponding to a particular clock signal and scheduled to occur at a time that can be determined from at least one attribute of the clock signal, such that clocked-scheduled events are distinguishable from time-scheduled events, and such that each and every transition of any clock signal need not be scheduled in the time-scheduled event data structure.
摘要翻译： 模拟系统，用于实现模拟方法的计算机产品，以及模拟具有至少一个元件和至少一个具有时钟属性的时钟信号的数字电路的方法。 该方法包括维护调度在特定模拟时间发生的时间安排事件的数据结构; 并且保持每个对应于特定时钟信号的时钟预定事件的数据结构，并且被调度为在可以根据时钟信号的至少一个属性确定的时间发生，使得计时事件与时间调度 事件，并且使得任何时钟信号的每个转换不需要在时间调度事件数据结构中调度。
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3.发明授权Method and system for modeling a bus for a system design incorporating one or more programmable processors 有权用于对包含一个或多个可编程处理器的系统设计的总线进行建模的方法和系统公开(公告)号：US08644305B2
公开(公告)日：2014-02-04
申请号：US12017939
申请日：2008-01-22
CPC分类号： G06F17/5031 , G06F2217/84
摘要： Systems and methods for modeling a bus for a system design are provided. In an embodiment, the method operates by accepting a virtual bus model, wherein the model simulates behavior for a bus master and slave device, such that the model accurately simulates the timing and behavior of the transfer of data from master to slave, and, from slave to master devices. The method routes a transaction issued by the master device to the slave device. The transaction has storage for transaction data, or a pointer to transaction data, to be transferred through the transaction. The transaction data is transferred in one or more data payloads and the sender of data sets the length of data payloads to be returned. The data payloads are sent from the sender of data to the receiver of data and may contain one or more bus data beats. This method accurately models the bus timing and behavior of the delivery of one or more data beats as one data payload.
摘要翻译： 提供了用于为系统设计建立总线的系统和方法。 在一个实施例中，该方法通过接受虚拟总线模型来操作，其中模型模拟总线主设备和从设备的行为，使得该模型精确地模拟从主设备到从设备的数据传输的定时和行为，以及从 从设备到主设备。 该方法将主设备发出的事务路由到从设备。 交易具有用于交易数据的存储，或者是通过交易传送的交易数据的指针。 交易数据在一个或多个数据有效载荷中传送，数据发送者设置要返回的数据有效载荷的长度。 数据有效载荷从数据的发送者发送到数据的接收器，并且可以包含一个或多个总线数据跳动。 该方法将一个或多个数据节拍的总线时序和行为精确地建模为一个数据有效载荷。
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公开(公告)号：US08463589B2
公开(公告)日：2013-06-11
申请号：US12159831
申请日：2007-07-30
CPC分类号： G06F17/5022 , G06F17/5009 , G06F2217/86
摘要： A method of transforming a provided virtual processor model to a user virtual processor model. Also a tool, e.g., provided as instructions for operating in a host computer system for converting a provided virtual processor model to a user virtual processor model. Also a method of specifying one or more characteristics of a target processor to transform a provided virtual processor model to a user virtual processor model that when operating in a c-simulation system, simulates the operation of the target processor. For example, a method of specifying one or more characteristics of instructions to transform a provided virtual processor model to a user virtual processor model.
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5.发明申请Method and System for Modeling a Bus for a System Design Incorporating One or More Programmable Processors 有权用于为集成一个或多个可编程处理器的系统设计的总线建模的方法和系统公开(公告)号：US20080235415A1
公开(公告)日：2008-09-25
申请号：US12017939
申请日：2008-01-22
IPC分类号： G06F13/42
CPC分类号： G06F17/5031 , G06F2217/84
摘要： Systems and methods for modeling a bus for a system design are provided. In an embodiment, the method operates by accepting a virtual bus model, wherein the model simulates behavior for a bus master and slave device, such that the model accurately simulates the timing and behavior of the transfer of data from master to slave, and, from slave to master devices. The method routes a transaction issued by the master device to the slave device. The transaction has storage for transaction data, or a pointer to transaction data, to be transferred through the transaction. The transaction data is transferred in one or more data payloads and the sender of data sets the length of data payloads to be returned. The data payloads are sent from the sender of data to the receiver of data and may contain one or more bus data beats. This method accurately models the bus timing and behavior of the delivery of one or more data beats as one data payload.
摘要翻译： 提供了用于为系统设计建立总线的系统和方法。 在一个实施例中，该方法通过接受虚拟总线模型来操作，其中模型模拟总线主设备和从设备的行为，使得该模型精确地模拟从主设备到从设备的数据传输的定时和行为，以及从 从设备到主设备。 该方法将主设备发出的事务路由到从设备。 交易具有用于交易数据的存储，或者是通过交易传送的交易数据的指针。 交易数据在一个或多个数据有效载荷中传送，数据发送者设置要返回的数据有效载荷的长度。 数据有效载荷从数据的发送者发送到数据的接收器，并且可以包含一个或多个总线数据跳动。 该方法将一个或多个数据节拍的总线时序和行为精确地建模为一个数据有效载荷。
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6.发明授权Hardware and software co-simulation including simulating the cache of a target processor 有权硬件和软件协同仿真，包括模拟目标处理器的缓存公开(公告)号：US06263302B1
公开(公告)日：2001-07-17
申请号：US09491390
申请日：2000-01-26
申请人： Graham R. Hellestrand , King Yin Cheung , James R. Torossian , Ricky L. K. Chan , Ming Chi Kam , Foo Ngok Yong
发明人： Graham R. Hellestrand , King Yin Cheung , James R. Torossian , Ricky L. K. Chan , Ming Chi Kam , Foo Ngok Yong
IPC分类号： G06F9455
CPC分类号： G06F11/261 , G06F8/30 , G06F9/455 , G06F17/50 , G06F17/5022 , G06F2217/68
摘要： A co-simulation design system that runs on a host computer system is described that includes a hardware simulator and a processor simulator coupled via an interface mechanism. The execution of a user program on a target processor that includes a cache is simulated by executing an analyzed version of the user program on the host computer system. The analysis adds timing information to the user program so that the processor simulator provides accurate timing information whenever the processor simulator interacts with the hardware simulator. The analysis also adds hooks to the user program such that executing the analyzed user program on the host computer system invokes a cache simulator that simulates operation of the cache.
摘要翻译： 描述了在主计算机系统上运行的协同仿真设计系统，其包括通过接口机制耦合的硬件模拟器和处理器模拟器。 通过在主计算机系统上执行用户程序的分析版本来模拟包括高速缓存的目标处理器上的用户程序的执行。 分析将定时信息添加到用户程序，以便每当处理器模拟器与硬件模拟器进行交互时，处理器模拟器提供准确的定时信息。 分析还向用户程序添加了钩子，使得在主计算机系统上执行分析的用户程序调用模拟高速缓存的操作的高速缓存模拟器。
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7.发明授权Hardware and software co-simulation including simulating a target processor using binary translation 有权硬件和软件协同仿真，包括使用二进制翻译模拟目标处理器公开(公告)号：US06751583B1
公开(公告)日：2004-06-15
申请号：US09933579
申请日：2001-08-20
IPC分类号： G06F9455
CPC分类号： G06F17/5022 , G06F2217/68
摘要： A co-simulation design system to simulate on a host an electronic system that includes target digital circuitry and a target processor with an accompanying user program. The system includes a processor simulator to simulate execution of the user program by executing host software that includes an analyzed version of the user program. The system further includes a hardware simulator to simulate the target digital circuitry and an interface mechanism that couples the hardware simulator with the processor simulator. The user program is provided in binary form. Determining the analyzed version of the user program includes decomposing the user program into linear blocks, translating each linear block of the user program into host code that simulate the operations of the linear block, storing the host code of each linear block in a host code buffer for the linear block, and adding timing information into the code in the host code buffer on the time it would take for the target processor to execute the user program. The timing information incorporates target processor instruction timing. Adding of timing information includes inserting dynamic hooks into the host code that during execution invoke dynamic mechanisms that may effect timing and that cannot be determined ahead of execution such that while the processor simulator executes the analyzed version of the user program, the processor simulator accumulates simulation time according to a simulation time frame, the accumulated simulation time accounting for the target processor instruction timing as if the user program was executing on the target processor.
摘要翻译： 一种协同仿真设计系统，用于在主机上模拟包括目标数字电路和具有伴随用户程序的目标处理器的电子系统。 该系统包括处理器模拟器，用于通过执行包括用户程序的分析版本的主机软件来模拟用户程序的执行。 该系统还包括用于模拟目标数字电路的硬件模拟器和将硬件模拟器与处理器模拟器耦合的接口机制。 用户程序以二进制形式提供。 确定用户程序的分析版本包括将用户程序分解为线性块，将用户程序的每个线性块转换成模拟线性块的操作的主机代码，将每个线性块的主机代码存储在主机代码缓冲器 对于线性块，并且在目标处理器执行用户程序所需的时间内将定时信息添加到主机代码缓冲器中的代码中。 定时信息包含目标处理器指令定时。 添加定时信息包括在主机代码中插入动态挂钩，在执行过程中调用可能影响时序的动态机制，并且无法在执行之前确定，以便在处理器模拟器执行用户程序的分析版本时，处理器模拟器累积模拟 时间根据仿真时间框架，累积的模拟时间占目标处理器指令定时，好像用户程序正在目标处理器上执行。
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公开(公告)号：US06584436B2
公开(公告)日：2003-06-24
申请号：US09820086
申请日：2001-03-27
IPC分类号： G06F1750
CPC分类号： G06F11/261 , G06F17/5022 , G06F2217/68
摘要： A co-simulation design system that runs on a host computer system is described that includes a hardware simulator and a processor simulator coupled via a interface mechanism. The execution of a user program is simulated by executing an analyzed version of the user program on the host computer system. The analysis adds timing information to the user program so that the processor simulator provides accurate timing information whenever the processor simulator interacts with the hardware simulator.
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9.发明授权Hardware and software co-simulation including executing an analyzed user program 有权硬件和软件协同仿真，包括执行分析的用户程序公开(公告)号：US06230114B1
公开(公告)日：2001-05-08
申请号：US09430855
申请日：1999-10-29
IPC分类号： G06F1750
CPC分类号： G06F11/261 , G06F17/5022 , G06F2217/68
摘要： A co-simulation design system that runs on a host computer system is described that includes a hardware simulator and a processor simulator coupled via a interface mechanism. The execution of a user program is simulated by executing an analyzed version of the user program on the host computer system. The analysis adds timing information to the user program so that the processor simulator provides accurate timing information whenever the processor simulator interacts with the hardware simulator.
摘要翻译： 描述了在主计算机系统上运行的协同仿真设计系统，其包括通过接口机制耦合的硬件模拟器和处理器模拟器。 通过在主计算机系统上执行用户程序的分析版本来模拟用户程序的执行。 分析将定时信息添加到用户程序，以便每当处理器模拟器与硬件模拟器进行交互时，处理器模拟器提供准确的定时信息。
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