公开(公告)号：US06594283B1

公开(公告)日：2003-07-15

申请号：US09203184

申请日：1998-11-30

申请人： Nigel Horspool ,  David Law ,  Quang Tran ,  Patrick Overs

发明人： Nigel Horspool ,  David Law ,  Quang Tran ,  Patrick Overs

IPC分类号： H04L12413

CPC分类号： H04L49/351

摘要： A network communications device is arranged to have a fast throughput of data packets. This is achieved by recognising that, in protocols such as Ethernet, the first symbols in a data packet do not carry any data and therefore do not necessarily require to be properly carried through a communications hub. Rather, a known number of symbols are discarded from the start of a packet on receipt and replaced on re-transmission. This discarding reduces the reception delays particularly in bussed-architecture repeaters where bus arbitration must take place for each received packet.

摘要翻译： 网络通信设备被布置为具有数据分组的快速吞吐量。 这通过认识到，在诸如以太网的协议中，数据分组中的第一个符号不携带任何数据，因此不一定需要通过通信集线器正确地传输。 相反，已知数量的符号从接收到的分组的开始被丢弃并且在重传时被替换。 这种丢弃减少了接收延迟，特别是在总线仲裁必须对每个接收的分组进行总线仲裁时。

公开(公告)号：US06184734B2

公开(公告)日：2001-02-06

申请号：US09230530

申请日：1999-05-17

申请人： Patrick Overs

发明人： Patrick Overs

IPC分类号： H03L706

CPC分类号： H04L7/0338 ,  H03K5/15093 ,  H03L7/00 ,  H04L7/046

摘要： A phase locked loop is provided that includes a phase comparator for receiving an incoming signal with which is desired to lock. A loop filter processes a current error signal. An integrator adjusts the output to account for the error. The phase comparator, loop filter and integrator are formed from logic elements.

摘要翻译： 提供了一种锁相环，其包括用于接收期望锁定的输入信号的相位比较器。 环路滤波器处理电流误差信号。 积分器调整输出以解决错误。 相位比较器，环路滤波器和积分器由逻辑元件形成。

公开(公告)号：US20070136708A1

公开(公告)日：2007-06-14

申请号：US11610943

申请日：2006-12-14

申请人： Patrick Overs ,  Nicholas Horne ,  Johann Ziegler

发明人： Patrick Overs ,  Nicholas Horne ,  Johann Ziegler

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F2217/62

摘要： A clock distribution approach includes distributing a clock signal from a clock tree to a first set of circuit elements characterized by a first circuit characteristic; and distributing a clock signal from a sub-tree of the clock tree to a second set of circuit elements characterized by a second circuit characteristic different from the first circuit characteristic.

摘要翻译： 时钟分配方法包括将时钟信号从时钟树分配到由第一电路特性表征的第一组电路元件; 以及将来自时钟树的子树的时钟信号分配到由与第一电路特性不同的第二电路特性表征的第二组电路元件。