公开(公告)号：US20130142003A1

公开(公告)日：2013-06-06

申请号：US13312679

申请日：2011-12-06

Applicant: Nishu Kohli ,  Robin M. Wilson

Inventor： Nishu Kohli ,  Robin M. Wilson

IPC: G11C8/18

CPC classification number: G11C8/18 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222

Abstract: A memory circuitry includes memory components operable in response to first edges of an internal clock; and internal clock generating circuitry to generate the internal clock in response to a system clock, wherein the first edges of the internal clock are generated in response to both a rising and a falling edge of the system clock.

Abstract translation: 存储器电路包括响应于内部时钟的第一边缘而可操作的存储器组件; 以及响应于系统时钟产生内部时钟的内部时钟产生电路，其中响应于系统时钟的上升沿和下降沿产生内部时钟的第一边缘。

公开(公告)号：US08730756B2

公开(公告)日：2014-05-20

申请号：US13312679

申请日：2011-12-06

Applicant: Nishu Kohli ,  Robin M. Wilson

Inventor： Nishu Kohli ,  Robin M. Wilson

IPC: G11C8/00

CPC classification number: G11C8/18 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222

Abstract: A memory circuitry includes memory components operable in response to first edges of an internal clock; and internal clock generating circuitry to generate the internal clock in response to a system clock, wherein the first edges of the internal clock are generated in response to both a rising and a falling edge of the system clock.

Abstract translation: 存储器电路包括响应于内部时钟的第一边缘而可操作的存储器组件; 以及响应于系统时钟产生内部时钟的内部时钟产生电路，其中响应于系统时钟的上升沿和下降沿产生内部时钟的第一边缘。