公开(公告)号：US20100093145A1

公开(公告)日：2010-04-15

申请号：US12636408

申请日：2009-12-11

申请人： Nobuo TSUBOI ,  Motoshige Igarashi

发明人： Nobuo TSUBOI ,  Motoshige Igarashi

IPC分类号： H01L21/8239

CPC分类号： H01L27/1104 ,  H01L27/11

摘要： A structure is adopted for a layout of an SRAM cell which provides a local wiring 3a between a gate 2a and gate 2b and connects an active region 1a and an active region 1b. This eliminates the necessity for providing a contact between the gate 2a and the gate 2b. Therefore, it is possible to reduce the size of a memory cell region C in a short side direction. Furthermore, a structure whereby a left end of a gate 2c is retreated from the gate 2a and a local wiring 3b which connects the active region 1b and gate 2c disposed in a diagonal direction is adopted. This allows the gate 2a to be shifted toward the center of the memory cell region C.

摘要翻译： 采用在栅极2a和栅极2b之间提供局部布线3a并连接有源区域1a和有源区域1b的SRAM单元布局的结构。 这消除了在栅极2a和栅极2b之间提供接触的必要性。 因此，可以在短边方向上减小存储单元区域C的尺寸。 此外，采用栅极2c的左端从栅极2a退出的结构和连接沿对角线方向设置的有源区域1b和栅极2c的局部布线3b。 这允许栅极2a朝向存储单元区域C的中心移动。

公开(公告)号：US20090026520A1

公开(公告)日：2009-01-29

申请号：US12237693

申请日：2008-09-25

申请人： Nobuo TSUBOI ,  Motoshige Igarashi

发明人： Nobuo TSUBOI ,  Motoshige Igarashi

IPC分类号： H01L47/00

CPC分类号： H01L27/1104 ,  H01L27/11

摘要： A structure is adopted for a layout of an SRAM cell which provides a local wiring 3a between a gate 2a and gate 2b and connects an active region 1a and an active region 1b. This eliminates the necessity for providing a contact between the gate 2a and the gate 2b. Therefore, it is possible to reduce the size of a memory cell region C in a short side direction. Furthermore, a structure whereby a left end of a gate 2c is retreated from the gate 2a and a local wiring 3b which connects the active region 1b and gate 2c disposed in a diagonal direction is adopted. This allows the gate 2a to be shifted toward the center of the memory cell region C.

摘要翻译： 采用在栅极2a和栅极2b之间提供局部布线3a并连接有源区域1a和有源区域1b的SRAM单元布局的结构。 这消除了在栅极2a和栅极2b之间提供接触的必要性。 因此，可以在短边方向上减小存储单元区域C的尺寸。 此外，采用栅极2c的左端从栅极2a退出的结构和连接沿对角线方向设置的有源区域1b和栅极2c的局部布线3b。 这允许栅极2a朝向存储单元区域C的中心移动。

公开(公告)号：US20110278592A1

公开(公告)日：2011-11-17

申请号：US13087118

申请日：2011-04-14

申请人： Nobuo TSUBOI ,  Masakazu OKADA

发明人： Nobuo TSUBOI ,  Masakazu OKADA

IPC分类号： H01L29/12 ,  H01L29/772 ,  H01L29/06

CPC分类号： H01L29/0696 ,  H01L27/0207 ,  H01L27/11807

摘要： A semiconductor device which is designed based on RDR, suppresses the occurrence of a trouble at the boundary between an active region and a power wire and therearound and is small in size and highly integrated. The semiconductor device includes a first conductive impurity region for functional elements which is formed over the main surface of a semiconductor substrate and a second conductive impurity region for power potential to which power potential is applied in at least one standard cell. It also includes insulating layers which are formed over the main surface of the semiconductor substrate and have throughholes reaching the main surface of the semiconductor substrate, and a conductive layer for contact formed in the throughholes of the insulating layers. The impurity region for functional elements and the impurity region for power potential are electrically coupled to each other through the conductive layer for contact which is formed astride the impurity region for functional elements and the impurity region for power potential.

摘要翻译： 基于RDR设计的半导体器件抑制在活性区域和电源线之间的边界处的麻烦的发生，并且尺寸小并且高度集成。 半导体器件包括形成在半导体衬底的主表面上的功能元件的第一导电杂质区域和用于在至少一个标准单元中施加功率电位的功率电位的第二导电杂质区域。 它还包括形成在半导体衬底的主表面上并具有到达半导体衬底的主表面的通孔和形成在绝缘层的通孔中的用于接触的导电层的绝缘层。 用于功能元件的杂质区域和功率电位的杂质区域通过形成跨越功能元件的杂质区域和功率电位的杂质区域的接触用导电层彼此电耦合。

公开(公告)号：US20120299064A1

公开(公告)日：2012-11-29

申请号：US13471997

申请日：2012-05-15

申请人： Nobuo TSUBOI

发明人： Nobuo TSUBOI

IPC分类号： H01L27/10

CPC分类号： H01L27/1104 ,  H01L21/76808 ,  H01L23/4827 ,  H01L23/50 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1116 ,  H01L2924/0002 ,  Y10S257/903 ,  H01L2924/00

摘要： A semiconductor device in which wirings are formed adequately and electrical couplings are made properly in an SRAM memory cell. In the SRAM memory cell of the semiconductor device, a via to be electrically coupled to a third wiring as a word line is directly coupled to a contact plug electrically coupled to the gate wiring part of an access transistor. Also, another via to be electrically coupled to the third wiring as the word line is directly coupled to a contact plug electrically coupled to the gate wiring part of another access transistor.

摘要翻译： 在SRAM存储单元中适当地形成布线的半导体器件和电耦合。 在半导体器件的SRAM存储单元中，要作为字线电耦合到第三布线的通孔直接耦合到电耦合到存取晶体管的栅极布线部分的接触插塞。 此外，当字线直接耦合到电耦合到另一个存取晶体管的栅极布线部分的接触插头时，另一通孔电耦合到第三布线。