公开(公告)号：US5671393A

公开(公告)日：1997-09-23

申请号：US717149

申请日：1996-09-20

申请人： Norihiro Yamaki ,  Noriyuki Takao ,  Hidetoshi Takano

发明人： Norihiro Yamaki ,  Noriyuki Takao ,  Hidetoshi Takano

IPC分类号： G06F15/16 ,  G06F13/18 ,  G06F15/177 ,  G06F13/16

CPC分类号： G06F13/18

摘要： A shared memory system and an arbitrating method and system. When the processing is distributed over a plurality of CPUs (e.g., CPUA and CPUB) and if it is desired that a shared memory is used to transfer data between the CPUs, a clock CKG indicating the CPUA access timing clock is generated. A gate signal G indicating the access right to the shared memory is generated in synchronism with the clock CKG. When either of the CPUs requests the access to the shared memory, it makes the corresponding chip select signal CSA.sup.- or CSB.sup.- L-level. The access right is always directed to the CPUA and switched to the CPUB in response to the access demand from the CPUB. After one access has completed, the CPUB makes CSB.sup.- H-level. Thus, the access right is switched to the CPUA. After one access has terminated, the CPUA makes CSA.sup.- H-level. If the CPUB requests the access at this time, the access right is switched to the CPUB. If the CPUB does not request the access, the access right is maintained at the CPUA. The CPUA and CPUB are synchronized with each other through a wait signal WAITA.sup.-. When the shared memory is to be accessed, no software is required. The speed of data transfer can be increased and the loads on the CPUs will not influence each other.

摘要翻译： 共享内存系统和仲裁方法和系统。 当处理分布在多个CPU（例如，CPUA和CPUB）上时，并且如果希望使用共享存储器在CPU之间传送数据，则生成指示CPUA访问定时时钟的时钟CKG。 与时钟CKG同步地产生指示到共享存储器的访问权限的门信号G. 当任一CPU请求访问共享存储器时，它使相应的芯片选择信号CSA或CSB-L级。 访问权限始终指向CPUA，并根据CPUB的访问需求切换到CPUB。 一次访问完成后，CPUB使CSB-H级。 因此，访问权限切换到CPUA。 一个访问终止后，CPUA使CSA-H级。 如果CPUB此时请求访问，则访问权限被切换到CPUB。 如果CPUB不请求访问，则CPUA将维护访问权限。 CPUA和CPUB通过等待信号WAITA-彼此同步。 当共享存储器被访问时，不需要软件。 可以提高数据传输的速度，并且CPU上的负载不会相互影响。

公开(公告)号：US07791946B2

公开(公告)日：2010-09-07

申请号：US12166288

申请日：2008-07-01

申请人： Keiichirou Kikuchi ,  Hiroaki Wada ,  Norihiro Yamaki

发明人： Keiichirou Kikuchi ,  Hiroaki Wada ,  Norihiro Yamaki

IPC分类号： G11C16/26

CPC分类号： G11C16/28

摘要： The present invention is directed to a semiconductor device having a non-volatile memory cell 18, and a readout circuit 102 which reads out data of the memory cell 18 DATA using a first data DATA1 obtained by sensing a first reference level REF1 for reading out the data of the memory cell 18 and a level of the memory cell 18 CORE and using a second data DATA2 obtained by sensing a second reference level REF2 for reading out the data of the memory cell 18 and the level of the memory cell 18 CORE, and to a controlling method for the same.

摘要翻译： 本发明涉及具有非易失性存储单元18的半导体器件，以及读出电路102，其使用通过感测第一参考电平REF1而获得的第一数据DATA1来读出存储单元18 DATA的数据， 存储单元18的数据和存储单元18的电平CORE，并且使用通过感测用于读出存储单元18的数据的第二参考电平REF2和存储单元18CORE的电平而获得的第二数据DATA2，以及 涉及其控制方法。