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公开(公告)号：US11749168B1
公开(公告)日：2023-09-05
申请号：US17857154
申请日：2022-07-04
发明人： Ho-Chun Chang , Che-Wei Yeh , Yu-Hsiang Wang , Keko-Chun Liang
IPC分类号： G09G3/20
CPC分类号： G09G3/2092 , G09G2300/0838 , G09G2310/0289
摘要： The disclosure provides a data receiver, including a first capacitor, a second capacitor, a first inverter and a second inverter. The first capacitor has a first terminal and a second terminal, and the first terminal receives a first input signal. The second capacitor has a third terminal and a fourth terminal, and the third terminal receives a second input signal. The first inverter has a first input terminal and a first output terminal. The second inverter has a second input terminal and a second output terminal. The first input terminal and the second output terminal are coupled to the second terminal of the first capacitor, and the second input terminal and the first output terminal are coupled to the fourth terminal of the second capacitor. The first output terminal generates a first output signal with a first output voltage, and the second output terminal generates a second output signal with a second output voltage.
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公开(公告)号：US11527195B2
公开(公告)日：2022-12-13
申请号：US17238179
申请日：2021-04-22
发明人： Che-Wei Yeh , Keko-Chun Liang , Yu-Hsiang Wang , Yong-Ren Fang , Yi-Chuan Liu
摘要： A display control system includes a plurality of driver circuits connected in series. A driver circuit among the plurality of driver circuits includes a receiver, a duty cycle correction circuit and a transmitter. The receiver is configured to receive a first signal from a previous driver circuit among the plurality of driver circuits. The duty cycle correction circuit, coupled to the receiver, is configured to adjust a duty cycle of the first signal to generate a second signal. The transmitter, coupled to the duty cycle correction circuit, is configured to transmit the second signal to a next driver circuit among the plurality of driver circuits.
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公开(公告)号：US20220254305A1
公开(公告)日：2022-08-11
申请号：US17721337
申请日：2022-04-14
发明人： Che-Wei Yeh , Keko-Chun Liang , Yu-Hsiang Wang , Yong-Ren Fang , Yi-Chuan Liu
IPC分类号： G09G3/32
摘要： A LED driving apparatus with clock embedded cascaded LED drivers is introduced, including: a plurality of LED drivers, wherein the first stage LED driver receives an original data signal and outputs a first data signal, the Nth stage LED driver receives a (N−1)th data signal and outputs a Nth data signal. The Nth stage LED driver includes a clock data recovery circuit generating a recovery clock signal and a recovery data signal according to the (N−1)th data signal; and a first transmitter outputting the Nth data signal according to the recovery clock signal and the recovery data signal.
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公开(公告)号：US11341904B2
公开(公告)日：2022-05-24
申请号：US17138772
申请日：2020-12-30
发明人： Che-Wei Yeh , Keko-Chun Liang , Yu-Hsiang Wang , Yong-Ren Fang , Yi-Chuan Liu
IPC分类号： G09G3/32
摘要： A LED driving apparatus with clock embedded cascaded LED drivers is introduced, including: a plurality of LED drivers, wherein the first stage LED driver receives an original data signal and outputs a first data signal, the Nth stage LED driver receives a (N−1)th data signal and outputs a Nth data signal. The Nth stage LED driver includes a clock data recovery circuit generating a recovery clock signal and a recovery data signal according to the (N−1)th data signal; and a first transmitter outputting the Nth data signal according to the recovery clock signal and the recovery data signal.
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公开(公告)号：US11295671B2
公开(公告)日：2022-04-05
申请号：US16827713
申请日：2020-03-24
发明人： Jhih-Siou Cheng , Po-Hsiang Fang , Chieh-An Lin , Keko-Chun Liang , Ju-Lin Huang
IPC分类号： G09G3/3258
摘要： A display driver and a display driving method are provided. The display driving is adapted for driving a display panel and sensing an electrical characteristic of the display panel. The display driver includes a first amplifier circuit. The first amplifier circuit is coupled to the display panel. The first amplifier circuit includes a first driving circuit, a first sensing circuit and a first operational amplifier. The first operational amplifier is coupled to the display panel through a first driving line and a first sensing line. The first driving circuit is configured to provide a first driving signal to the display panel through the first operational amplifier and the first driving line during a driving period. The first sensing circuit is configured to receive a first sensing signal from the display panel through the first operational amplifier and the first sensing line during a first sensing period.
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公开(公告)号：US20210118359A1
公开(公告)日：2021-04-22
申请号：US17138772
申请日：2020-12-30
发明人： Che-Wei Yeh , Keko-Chun Liang , Yu-Hsiang Wang , Yong-Ren Fang , Yi-Chuan Liu
IPC分类号： G09G3/32
摘要： A LED driving apparatus with clock embedded cascaded LED drivers is introduced, including: a plurality of LED drivers, wherein the first stage LED driver receives an original data signal and outputs a first data signal, the Nth stage LED driver receives a (N−1)th data signal and outputs a Nth data signal. The Nth stage LED driver includes a clock data recovery circuit generating a recovery clock signal and a recovery data signal according to the (N−1)th data signal; and a first transmitter outputting the Nth data signal according to the recovery clock signal and the recovery data signal.
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公开(公告)号：US20210049952A1
公开(公告)日：2021-02-18
申请号：US16841686
申请日：2020-04-07
发明人： Che-Wei Yeh , Keko-Chun Liang , Yu-Hsiang Wang , Yong-Ren Fang , Yi-Chuan Liu
IPC分类号： G09G3/32
摘要： A LED driving apparatus with clock embedded cascaded LED drivers is introduced, including: a plurality of LED drivers, wherein the first stage LED driver receives an original display data signal and outputs a first display data signal, the Nth stage LED driver receives a (N−1)th display data signal and outputs a Nth display data signal. The Nth stage LED driver includes a clock data recovery circuit generating a recovery clock signal and a recovery data signal according to a first phase difference between the (N−1)th display data signal and the recovery clock signal; and a first transmitter outputting the Nth display data signal according to the recovery clock signal and the recovery data signal.
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公开(公告)号：US10725486B2
公开(公告)日：2020-07-28
申请号：US16052654
申请日：2018-08-02
发明人： Yong-Ren Fang , Shen-Iuan Liu , Ju-Lin Huang , Tzu-Chien Tzeng , Keko-Chun Liang , Yu-Hsiang Wang , Che-Wei Yeh
IPC分类号： G05F1/46 , H03K5/24 , G01R19/165
摘要： A reference voltage generator includes a detecting voltage provider, a comparator, and a core circuit. The detecting voltage provider provides a detecting voltage with a first voltage level corresponding to a voltage coefficient. The comparator compares the first voltage level of the detecting voltage with a plurality of sampled amplitudes of an input signal to respectively generate a plurality of comparison results. The core circuit is used to: collect a plurality of first comparison results associated with a current received bit of a preset value from the comparison results; take the voltage coefficient as a first boundary voltage coefficient in response to the first comparison results satisfying a first condition; take the voltage coefficient as a second boundary voltage coefficient in response to the first comparison results satisfying a second condition. The reference circuit generates a reference voltage according to the first and second boundary voltage coefficients.
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公开(公告)号：US10121777B2
公开(公告)日：2018-11-06
申请号：US15275492
申请日：2016-09-26
发明人： Chun-Yu Lin , Jie-Ting Chen , Ming-Dou Ker , Tzu-Chien Tzeng , Keko-Chun Liang , Ju-Lin Huang
摘要： A silicon controlled rectifier including a semiconductor substrate, first and second semiconductor wells, first and second semiconductor regions, third and fourth semiconductor regions and a silicide layer is provided. The first and the second semiconductor wells are formed in the semiconductor substrate. The first and the second semiconductor regions are respectively formed in the first and the second semiconductor wells in spaced apart relation. The third and the fourth semiconductor regions are respectively formed in the first and the second semiconductor wells. The silicide layer is formed on the third and the fourth semiconductor regions. The silicon controlled rectifier is at least suitable for high frequency circuit application. The silicon controlled rectifier has a relatively low trigger voltage, a relatively high electrostatic discharge level, and a relatively low capacitance.
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公开(公告)号：US20140015587A1
公开(公告)日：2014-01-16
申请号：US13792245
申请日：2013-03-11
发明人： Cheng-Hung Chen , Ju-Lin Huang , Keko-Chun Liang
IPC分类号： H03K3/012
CPC分类号： H03K3/012 , H03K3/356182
摘要： A level shifting circuit with dynamic control includes a dynamic controller and a level shifter. The dynamic controller outputs a dynamic voltage and an output data signal. The level shifter under control by the dynamic controller includes an input signal receiver, an output signal generator, and a bias current controller, which are coupled in series between a ground voltage and a high level voltage. The input signal receiver receives the output data signal of the dynamic controller and the output signal generator produces a level-shifted data signal according to the input data signal. The bias current controller controlled by the dynamic voltage is at a first current-output capability when the level-shifted data signal is at a stable stage and at a second current-output capability when the level-shifted data signal is at an unstable stage. The first current-output capability is greater than the second current-output capability.
摘要翻译： 具有动态控制的电平移动电路包括动态控制器和电平转换器。 动态控制器输出动态电压和输出数据信号。 由动态控制器控制的电平移位器包括输入信号接收器，输出信号发生器和偏置电流控制器，它们串联在接地电压和高电平电压之间。 输入信号接收器接收动态控制器的输出数据信号，输出信号发生器根据输入数据信号产生电平移位数据信号。 当电平移位数据信号处于不稳定阶段时，当电平移位数据信号处于稳定级并处于第二电流输出能力时，由动态电压控制的偏置电流控制器处于第一电流输出能力。 第一个电流输出能力大于第二个电流输出能力。
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