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公开(公告)号：US20190113939A1
公开(公告)日：2019-04-18
申请号：US16052654
申请日：2018-08-02
Applicant: Novatek Microelectronics Corp.
Inventor： Yong-Ren Fang , Shen-Iuan Liu , Ju-Lin Huang , Tzu-Chien Tzeng , Keko-Chun Liang , Yu-Hsiang Wang , Che-Wei Yeh
IPC: G05F1/46 , H03K5/24 , G01R19/165
CPC classification number: G05F1/46 , G01R19/16528 , H03K5/24
Abstract: A reference voltage generator includes a detecting voltage provider, a comparator, and a core circuit. The detecting voltage provider provides a detecting voltage with a first voltage level corresponding to a voltage coefficient. The comparator compares the first voltage level of the detecting voltage with a plurality of sampled amplitudes of an input signal to respectively generate a plurality of comparison results. The core circuit is used to: collect a plurality of first comparison results associated with a current received bit of a preset value from the comparison results; take the voltage coefficient as a first boundary voltage coefficient in response to the first comparison results satisfying a first condition; take the voltage coefficient as a second boundary voltage coefficient in response to the first comparison results satisfying a second condition. The reference circuit generates a reference voltage according to the first and second boundary voltage coefficients.
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公开(公告)号：US10725486B2
公开(公告)日：2020-07-28
申请号：US16052654
申请日：2018-08-02
Applicant: Novatek Microelectronics Corp.
Inventor： Yong-Ren Fang , Shen-Iuan Liu , Ju-Lin Huang , Tzu-Chien Tzeng , Keko-Chun Liang , Yu-Hsiang Wang , Che-Wei Yeh
IPC: G05F1/46 , H03K5/24 , G01R19/165
Abstract: A reference voltage generator includes a detecting voltage provider, a comparator, and a core circuit. The detecting voltage provider provides a detecting voltage with a first voltage level corresponding to a voltage coefficient. The comparator compares the first voltage level of the detecting voltage with a plurality of sampled amplitudes of an input signal to respectively generate a plurality of comparison results. The core circuit is used to: collect a plurality of first comparison results associated with a current received bit of a preset value from the comparison results; take the voltage coefficient as a first boundary voltage coefficient in response to the first comparison results satisfying a first condition; take the voltage coefficient as a second boundary voltage coefficient in response to the first comparison results satisfying a second condition. The reference circuit generates a reference voltage according to the first and second boundary voltage coefficients.
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Patent Agency Ranking
公开(公告)号：US11128304B1
公开(公告)日：2021-09-21
申请号：US16879768
申请日：2020-05-21
Applicant: Novatek Microelectronics Corp.
Inventor： Yun-Sheng Yao , Shen-Iuan Liu , Yen-Long Lee , Peng-Yu Chen , Chih-Hao Huang , Yao-Hung Kuo
Abstract: A clock and data recovery device and a jitter tolerance enhancement method thereof are provided. The clock and data recovery device includes a clock and data recovery circuit and a jitter tolerance enhancement circuit. A data input terminal of the clock and data recovery circuit is suitable for receiving a data signal. The clock and data recovery circuit recovers the data signal to a clock. The jitter tolerance enhancement circuit is coupled to the data input terminal of the clock and data recovery circuit to receive the data signal. The jitter tolerance enhancement circuit detects a correlation between the data signal and the clock and correspondingly adjusts a loop gain of the clock and data recovery circuit according to the correlation.
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公开(公告)号：US20180198597A1
公开(公告)日：2018-07-12
申请号：US15863983
申请日：2018-01-08
Applicant: Novatek Microelectronics Corp.
Inventor： Chang-Cheng Huang , Shen-Iuan Liu , Ju-Lin Huang , Tzu-Chien Tzeng , Keko-Chun Liang , Yu-Hsiang Wang , Che-Wei Yeh
CPC classification number: H04L7/0016 , H03L7/0807 , H03L7/087 , H03L7/0891 , H03L7/0898 , H03L7/091 , H03L7/093 , H03L2207/06
Abstract: A clock and data recovery circuit with jitter tolerance enhancement is provided. The CDR circuit includes: a bang-bang phase detector, a digital filter, a digitally controlled oscillator, and an adaptive loop gain control circuit. The CDR circuit detects a loop bandwidth variation and adjusts the loop bandwidth of CDR circuit by adjusting proportional path and integral path gain factors of the digital filter of the CDR circuit. The loop gain controller uses two methods to adjust the loop gain in CDR circuit: bang-bang adjusting method and linear adjusting method.
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公开(公告)号：US20200007085A1
公开(公告)日：2020-01-02
申请号：US16021032
申请日：2018-06-28
Applicant: NOVATEK Microelectronics Corp.
Inventor： Cheng-En Hsieh , Shen-Iuan Liu , Tzu-Chien Tzeng , Jin-Yi Lin , Kuo-Sheng Huang , Ju-Lin Huang
Abstract: A dynamic amplifier includes a first output capacitor, a first switch, a current source, a second switch, a voltage detector, a third switch and a level shifter. The first switch is coupled between a first terminal of the first output capacitor and a voltage detection node. The second switch is coupled to the current source and the voltage detection node. The voltage detector is coupled to the voltage detection node and the first switch. The third switch is coupled between the voltage detection node and a power source. The level shifter is coupled to a second terminal of the first output capacitor.
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公开(公告)号：US10594264B2
公开(公告)日：2020-03-17
申请号：US16021032
申请日：2018-06-28
Applicant: NOVATEK Microelectronics Corp.
Inventor： Cheng-En Hsieh , Shen-Iuan Liu , Tzu-Chien Tzeng , Jin-Yi Lin , Kuo-Sheng Huang , Ju-Lin Huang
Abstract: A dynamic amplifier includes a first output capacitor, a first switch, a current source, a second switch, a voltage detector, a third switch and a level shifter. The first switch is coupled between a first terminal of the first output capacitor and a voltage detection node. The second switch is coupled to the current source and the voltage detection node. The voltage detector is coupled to the voltage detection node and the first switch. The third switch is coupled between the voltage detection node and a power source. The level shifter is coupled to a second terminal of the first output capacitor.
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公开(公告)号：US10256967B2
公开(公告)日：2019-04-09
申请号：US15863983
申请日：2018-01-08
Applicant: Novatek Microelectronics Corp.
Inventor： Chang-Cheng Huang , Shen-Iuan Liu , Ju-Lin Huang , Tzu-Chien Tzeng , Keko-Chun Liang , Yu-Hsiang Wang , Che-Wei Yeh
Abstract: A clock and data recovery circuit with jitter tolerance enhancement is provided. The CDR circuit includes: a bang-bang phase detector, a digital filter, a digitally controlled oscillator, and an adaptive loop gain control circuit. The CDR circuit detects a loop bandwidth variation and adjusts the loop bandwidth of CDR circuit by adjusting proportional path and integral path gain factors of the digital filter of the CDR circuit. The loop gain controller uses two methods to adjust the loop gain in CDR circuit: bang-bang adjusting method and linear adjusting method.
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