公开(公告)号：US20210281839A1

公开(公告)日：2021-09-09

申请号：US17098699

申请日：2020-11-16

Applicant: OL Security Limited Liability Company

Inventor： Ujval J. Kapasi ,  Amit Gulati ,  John Seivers ,  Yipeng Liu ,  Dan Miller

IPC: H04N19/115 ,  H04N19/56 ,  H04N19/61 ,  H04N19/43 ,  H04N19/433 ,  H04N19/436 ,  H04N19/53 ,  H04N19/533 ,  H04N19/176 ,  H04N19/46 ,  H04N19/51

Abstract: A method operates within an integrated circuit having a plurality of processing lanes. For each of a first and second processing lanes, the method determines a number of packed data words among one or more packed data words associated with the respective processing lane, associates the number of packed data words with a used field of the processing lane, wherein the used field indicates the number of packed data words in the processing lane; and stores the one or more packed data words in a variable record length memory based, at least in part, on the used field of the processing lane.

公开(公告)号：US09667962B2

公开(公告)日：2017-05-30

申请号：US14513191

申请日：2014-10-13

Applicant: OL Security Limited Liability Company

Inventor： Ujval J. Kapasi ,  Amit Gulati ,  John Seivers ,  Yipeng Liu ,  Dan Miller

IPC: H04N7/12 ,  H04J3/04 ,  H04N11/04 ,  H04N19/583 ,  H04N19/46 ,  H04N19/176 ,  H04N19/56 ,  H04N19/61 ,  H04N19/43 ,  H04N19/433 ,  H04N19/436 ,  H04N19/53 ,  H04N19/533 ,  H04N19/51

CPC classification number: H04N19/115 ,  H04N19/176 ,  H04N19/43 ,  H04N19/433 ,  H04N19/436 ,  H04N19/46 ,  H04N19/51 ,  H04N19/53 ,  H04N19/533 ,  H04N19/56 ,  H04N19/61

Abstract: A method operates within an integrated circuit device having a plurality of processing lanes. The method determines a first number of packs among one or more first packs associated with a first processing lane of the plurality of processing lanes, associates the first number of packs with a first used field of the first processing lane, determines a second number of packs among one or more second packs associated with a second processing lane of the plurality of processing lanes, and associates the second number of packs with a second used field of the second processing lane.

公开(公告)号：US11665342B2

公开(公告)日：2023-05-30

申请号：US17098699

申请日：2020-11-16

Applicant: OL Security Limited Liability Company

Inventor： Ujval J. Kapasi ,  Amit Gulati ,  John Seivers ,  Yipeng Liu ,  Dan Miller

IPC: H04N19/115 ,  H04N19/56 ,  H04N19/61 ,  H04N19/43 ,  H04N19/433 ,  H04N19/436 ,  H04N19/53 ,  H04N19/533 ,  H04N19/176 ,  H04N19/46 ,  H04N19/51

CPC classification number: H04N19/115 ,  H04N19/176 ,  H04N19/43 ,  H04N19/433 ,  H04N19/436 ,  H04N19/46 ,  H04N19/51 ,  H04N19/53 ,  H04N19/533 ,  H04N19/56 ,  H04N19/61

Abstract: A method operates within an integrated circuit having a plurality of processing lanes. For each of a first and second processing lanes, the method determines a number of packed data words among one or more packed data words associated with the respective processing lane, associates the number of packed data words with a used field of the processing lane, wherein the used field indicates the number of packed data words in the processing lane; and stores the one or more packed data words in a variable record length memory based, at least in part, on the used field of the processing lane.

公开(公告)号：US20170264899A1

公开(公告)日：2017-09-14

申请号：US15607474

申请日：2017-05-27

Applicant: OL Security Limited Liability Company

Inventor： Ujval J. Kapasi ,  Amit Gulati ,  John Seivers ,  Yipeng Liu ,  Dan Miller

IPC: H04N19/115 ,  H04N19/176 ,  H04N19/43 ,  H04N19/433 ,  H04N19/436 ,  H04N19/46 ,  H04N19/51 ,  H04N19/53 ,  H04N19/533 ,  H04N19/56 ,  H04N19/61

Abstract: A method operates within an integrated circuit having a plurality of processing lanes. For each of a first and second processing lanes, the method determines a number of packed data words among one or more packed data words associated with the respective processing lane, associates the number of packed data words with a used field of the processing lane, wherein the used field indicates the number of packed data words in the processing lane; and stores the one or more packed data words in a variable record length memory based, at least in part, on the used field of the processing lane.