ELEVATOR SYSTEM WITH BRAKE FAILURE RESPONSES

    公开(公告)号:US20240383724A1

    公开(公告)日:2024-11-21

    申请号:US18318664

    申请日:2023-05-16

    Abstract: A method of operating an elevator system is provided and includes recognizing that brakes of an elevator car fail to drop upon brake power being removed, temporarily hovering the elevator car in place to allow the elevator car to be emptied, controllably moving the elevator car in a direction of imbalance, which is defined in terms of relative weights of the elevator car and a counter-weight and torque applied to the elevator car for driving the elevator car upwardly or downwardly, to either a top or a bottom of a hoistway and confirming that the brakes are failing to drop or provide sufficient holding torque.

    ELEVATOR BRAKE CONTROL
    4.
    发明申请

    公开(公告)号:US20210101777A1

    公开(公告)日:2021-04-08

    申请号:US16592180

    申请日:2019-10-03

    Abstract: An illustrative example embodiment of an elevator brake control device includes at least one primary switch configured to selectively conduct current for lifting all of a plurality of brake applicators. A plurality of secondary switches are each associated with one of the brake applicators. Each of the secondary switches is configured to selectively conduct current for lifting the associated one of the brake applicators. The plurality of secondary switches are between the primary switch and the associated one of the brake applicators.

    ELEVATOR MACHINE BRAKING
    5.
    发明公开

    公开(公告)号:US20240275314A1

    公开(公告)日:2024-08-15

    申请号:US18166513

    申请日:2023-02-09

    CPC classification number: H02P3/22 B66B1/06 B66B11/043

    Abstract: An elevator drive configured to control power to an elevator motor includes a plurality of first (upper) inverter switches and a plurality of second (lower) inverter switches. A processor is configured to provide control signals to control operation of the inverter switches. A first signal buffer between the processor and the inverter switches is configured to selectively prevent any control signals from turning on any of the inverter switches when the motor should not receive power. A second signal buffer between the processor and the inverter switches is configured to selectively bypass the first signal buffer, prevent any control signals from turning on the first inverter switches, and allow a control signal from the processor to turn on the second inverter switches to provide motor braking.

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