公开(公告)号：US20080284468A1

公开(公告)日：2008-11-20

申请号：US11749002

申请日：2007-05-15

申请人： Oleg Drapkin ,  Grigori Temkine ,  Marcus Ng ,  Kevin Yikai Liang ,  Arvind Bomdica ,  Siji Menokki Kandiyil ,  Ming So ,  Samu Suryanarayana

发明人： Oleg Drapkin ,  Grigori Temkine ,  Marcus Ng ,  Kevin Yikai Liang ,  Arvind Bomdica ,  Siji Menokki Kandiyil ,  Ming So ,  Samu Suryanarayana

IPC分类号： H03K19/0175

CPC分类号： H03K19/00384 ,  H03K17/223 ,  H04L25/028

摘要： An integrated circuit is capable of controlling a communication signal by using power ramp controlled communication buffer logic to generate an outgoing communication signal based on a detected voltage on a voltage source. The voltage source is necessary to supply power for power ramp controlled communication buffer logic. The voltage on the voltage source may be detected using power ramp sensor logic. The outgoing communication signal is based on a core logic output signal if the detected voltage is greater than or equal to a predetermined voltage level. If, the detected voltage is less than the predetermined voltage level, the outgoing communication signal is predetermined to be one of: a tristate outgoing communication signal, a logic one outgoing communication signal and a logic zero outgoing communication signal. Power ramp controlled communication buffer logic may also generate a core logic input signal based on an incoming communication signal in response to the detected voltage.

摘要翻译： 集成电路能够通过使用功率斜坡控制的通信缓冲器逻辑来控制通信信号，以基于电压源上的检测到的电压来产生输出通信信号。 为电源斜坡控制的通信缓冲逻辑电源供电需要电压源。 可以使用功率斜坡传感器逻辑来检测电压源上的电压。 如果检测到的电压大于或等于预定电压电平，则输出通信信号基于核心逻辑输出信号。 如果检测到的电压小于预定电压电平，则将输出通信信号预定为三态输出通信信号，逻辑1输出通信信号和逻辑零输出通信信号之一。 功率斜坡控制通信缓冲器逻辑还可以响应于检测到的电压而基于输入通信信号生成核心逻辑输入信号。

公开(公告)号：US08570067B2

公开(公告)日：2013-10-29

申请号：US11749002

申请日：2007-05-15

申请人： Oleg Drapkin ,  Grigori Temkine ,  Marcus Ng ,  Kevin Yikai Liang ,  Arvind Bomdica ,  Siji Menokki Kandiyil ,  Ming So ,  Samu Suryanarayana

发明人： Oleg Drapkin ,  Grigori Temkine ,  Marcus Ng ,  Kevin Yikai Liang ,  Arvind Bomdica ,  Siji Menokki Kandiyil ,  Ming So ,  Samu Suryanarayana

IPC分类号： H03K19/0175

CPC分类号： H03K19/00384 ,  H03K17/223 ,  H04L25/028

摘要： An integrated circuit is capable of controlling a communication signal by using power ramp controlled communication buffer logic to generate an outgoing communication signal based on a detected voltage on a voltage source. The voltage source is necessary to supply power for power ramp controlled communication buffer logic. The voltage on the voltage source may be detected using power ramp sensor logic. The outgoing communication signal is based on a core logic output signal if the detected voltage is greater than or equal to a predetermined voltage level. If, the detected voltage is less than the predetermined voltage level, the outgoing communication signal is predetermined to be one of: a tristate outgoing communication signal, a logic one outgoing communication signal and a logic zero outgoing communication signal. Power ramp controlled communication buffer logic may also generate a core logic input signal based on an incoming communication signal in response to the detected voltage.

摘要翻译： 集成电路能够通过使用功率斜坡控制的通信缓冲器逻辑来控制通信信号，以基于电压源上的检测到的电压来产生输出通信信号。 为电源斜坡控制的通信缓冲逻辑电源供电需要电压源。 可以使用功率斜坡传感器逻辑检测电压源上的电压。 如果检测到的电压大于或等于预定电压电平，则输出通信信号基于核心逻辑输出信号。 如果检测到的电压小于预定电压电平，则将输出通信信号预定为三态输出通信信号，逻辑1输出通信信号和逻辑零输出通信信号之一。 功率斜坡控制通信缓冲器逻辑还可以响应于检测到的电压而基于输入通信信号生成核心逻辑输入信号。

公开(公告)号：US07659768B2

公开(公告)日：2010-02-09

申请号：US12339800

申请日：2008-12-19

申请人： Samu Suryanarayana ,  Arvind Bomdica ,  Yikai Liang

发明人： Samu Suryanarayana ,  Arvind Bomdica ,  Yikai Liang

IPC分类号： H03L5/00

CPC分类号： H03K3/35613 ,  H03K3/012

摘要： A level shifting circuit includes a first stage and a second stage. The first stage and second stage are operatively coupled to a first and second power supply. The first stage translates a differential input voltage into an intermediate differential voltage. The second stage translates the intermediate differential voltage into a differential output voltage and provides feedback to the first stage in response to translating the intermediate differential voltage. The first stage reduces current flow between the first and second power supply through the second stage in response to the feedback.

摘要翻译： 电平移位电路包括第一级和第二级。 第一级和第二级可操作地耦合到第一和第二电源。 第一级将差分输入电压转换成中间差分电压。 第二级将中间差分电压转换成差分输出电压，并响应于平移中间差分电压而向第一级提供反馈。 响应于反馈，第一级减少通过第二级的第一和第二电源之间的电流。

公开(公告)号：US20090167405A1

公开(公告)日：2009-07-02

申请号：US12339800

申请日：2008-12-19

申请人： Samu Suryanarayana ,  Arvind Bomdica ,  Yikai Liang

发明人： Samu Suryanarayana ,  Arvind Bomdica ,  Yikai Liang

IPC分类号： H03L5/00

CPC分类号： H03K3/35613 ,  H03K3/012

摘要： A level shifting circuit includes a first stage and a second stage. The first stage and second stage are operatively coupled to a first and second power supply. The first stage translates a differential input voltage into an intermediate differential voltage. The second stage translates the intermediate differential voltage into a differential output voltage and provides feedback to the first stage in response to translating the intermediate differential voltage. The first stage reduces current flow between the first and second power supply through the second stage in response to the feedback.

摘要翻译： 电平移位电路包括第一级和第二级。 第一级和第二级可操作地耦合到第一和第二电源。 第一级将差分输入电压转换成中间差分电压。 第二级将中间差分电压转换成差分输出电压，并响应于平移中间差分电压而向第一级提供反馈。 响应于反馈，第一级减少通过第二级的第一和第二电源之间的电流。