公开(公告)号：US20080284468A1

公开(公告)日：2008-11-20

申请号：US11749002

申请日：2007-05-15

申请人： Oleg Drapkin ,  Grigori Temkine ,  Marcus Ng ,  Kevin Yikai Liang ,  Arvind Bomdica ,  Siji Menokki Kandiyil ,  Ming So ,  Samu Suryanarayana

发明人： Oleg Drapkin ,  Grigori Temkine ,  Marcus Ng ,  Kevin Yikai Liang ,  Arvind Bomdica ,  Siji Menokki Kandiyil ,  Ming So ,  Samu Suryanarayana

IPC分类号： H03K19/0175

CPC分类号： H03K19/00384 ,  H03K17/223 ,  H04L25/028

摘要： An integrated circuit is capable of controlling a communication signal by using power ramp controlled communication buffer logic to generate an outgoing communication signal based on a detected voltage on a voltage source. The voltage source is necessary to supply power for power ramp controlled communication buffer logic. The voltage on the voltage source may be detected using power ramp sensor logic. The outgoing communication signal is based on a core logic output signal if the detected voltage is greater than or equal to a predetermined voltage level. If, the detected voltage is less than the predetermined voltage level, the outgoing communication signal is predetermined to be one of: a tristate outgoing communication signal, a logic one outgoing communication signal and a logic zero outgoing communication signal. Power ramp controlled communication buffer logic may also generate a core logic input signal based on an incoming communication signal in response to the detected voltage.

摘要翻译： 集成电路能够通过使用功率斜坡控制的通信缓冲器逻辑来控制通信信号，以基于电压源上的检测到的电压来产生输出通信信号。 为电源斜坡控制的通信缓冲逻辑电源供电需要电压源。 可以使用功率斜坡传感器逻辑来检测电压源上的电压。 如果检测到的电压大于或等于预定电压电平，则输出通信信号基于核心逻辑输出信号。 如果检测到的电压小于预定电压电平，则将输出通信信号预定为三态输出通信信号，逻辑1输出通信信号和逻辑零输出通信信号之一。 功率斜坡控制通信缓冲器逻辑还可以响应于检测到的电压而基于输入通信信号生成核心逻辑输入信号。

公开(公告)号：US08570067B2

公开(公告)日：2013-10-29

申请号：US11749002

申请日：2007-05-15

申请人： Oleg Drapkin ,  Grigori Temkine ,  Marcus Ng ,  Kevin Yikai Liang ,  Arvind Bomdica ,  Siji Menokki Kandiyil ,  Ming So ,  Samu Suryanarayana

发明人： Oleg Drapkin ,  Grigori Temkine ,  Marcus Ng ,  Kevin Yikai Liang ,  Arvind Bomdica ,  Siji Menokki Kandiyil ,  Ming So ,  Samu Suryanarayana

IPC分类号： H03K19/0175

CPC分类号： H03K19/00384 ,  H03K17/223 ,  H04L25/028

摘要： An integrated circuit is capable of controlling a communication signal by using power ramp controlled communication buffer logic to generate an outgoing communication signal based on a detected voltage on a voltage source. The voltage source is necessary to supply power for power ramp controlled communication buffer logic. The voltage on the voltage source may be detected using power ramp sensor logic. The outgoing communication signal is based on a core logic output signal if the detected voltage is greater than or equal to a predetermined voltage level. If, the detected voltage is less than the predetermined voltage level, the outgoing communication signal is predetermined to be one of: a tristate outgoing communication signal, a logic one outgoing communication signal and a logic zero outgoing communication signal. Power ramp controlled communication buffer logic may also generate a core logic input signal based on an incoming communication signal in response to the detected voltage.

摘要翻译： 集成电路能够通过使用功率斜坡控制的通信缓冲器逻辑来控制通信信号，以基于电压源上的检测到的电压来产生输出通信信号。 为电源斜坡控制的通信缓冲逻辑电源供电需要电压源。 可以使用功率斜坡传感器逻辑检测电压源上的电压。 如果检测到的电压大于或等于预定电压电平，则输出通信信号基于核心逻辑输出信号。 如果检测到的电压小于预定电压电平，则将输出通信信号预定为三态输出通信信号，逻辑1输出通信信号和逻辑零输出通信信号之一。 功率斜坡控制通信缓冲器逻辑还可以响应于检测到的电压而基于输入通信信号生成核心逻辑输入信号。

公开(公告)号：US20080157817A1

公开(公告)日：2008-07-03

申请号：US12046887

申请日：2008-03-12

申请人： Oleg Drapkin ,  Grigori Temkine ,  Arvind Bomdica ,  Kevin Liang

发明人： Oleg Drapkin ,  Grigori Temkine ,  Arvind Bomdica ,  Kevin Liang

IPC分类号： H03K19/0185

CPC分类号： H03K19/0185 ,  H03K19/094

摘要： An input signal is routed to a first logic one reference signal generator or alternatively routed to a second logic one reference signal generator based at least one a voltage level of the input signal. When the voltage level of the input signal is less than a threshold value, the first logic one reference signal generator selectively generates a first logic one reference signal. When the voltage level of the input signal is greater than or equal to the threshold value, the second logic one reference signal generator alternatively generates a second logic one reference signal. The first and second logic one reference signals may be used to control a first voltage scaling circuit that drives a scaled output signal having a logic one value corresponding to the voltage level of the first logic one reference signal.

摘要翻译： 输入信号被路由到第一逻辑一个参考信号发生器，或者基于输入信号的至少一个电压电平路由到第二逻辑1参考信号发生器。 当输入信号的电压电平小于阈值时，第一逻辑1参考信号发生器选择性地产生第一逻辑1参考信号。 当输入信号的电压电平大于或等于阈值时，第二逻辑1参考信号发生器交替产生第二逻辑1参考信号。 第一和第二逻辑一个参考信号可以用于控制驱动具有对应于第一逻辑1参考信号的电压电平的逻辑1值的定标输出信号的第一电压缩放电路。

公开(公告)号：US20080054942A1

公开(公告)日：2008-03-06

申请号：US11469311

申请日：2006-08-31

申请人： Oleg Drapkin ,  Grigori Temkine ,  Arvind Bomdica ,  Kevin Liang

发明人： Oleg Drapkin ,  Grigori Temkine ,  Arvind Bomdica ,  Kevin Liang

IPC分类号： H03K19/0185

CPC分类号： H03K19/0185 ,  H03K19/094

摘要： An input signal is routed to a first logic one reference signal generator or alternatively routed to a second logic one reference signal generator based at least one a voltage level of the input signal. When the voltage level of the input signal is less than a threshold value, the first logic one reference signal generator selectively generates a first logic one reference signal. When the voltage level of the input signal is greater than or equal to the threshold value, the second logic one reference signal generator alternatively generates a second logic one reference signal. The first and second logic one reference signals may be used to control a first voltage scaling circuit that drives a scaled output signal having a logic one value corresponding to the voltage level of the first logic one reference signal.

公开(公告)号：US07710150B2

公开(公告)日：2010-05-04

申请号：US12046887

申请日：2008-03-12

申请人： Oleg Drapkin ,  Grigori Temkine ,  Arvind Bomdica ,  Kevin Liang

发明人： Oleg Drapkin ,  Grigori Temkine ,  Arvind Bomdica ,  Kevin Liang

IPC分类号： H03K19/0175

CPC分类号： H03K19/0185 ,  H03K19/094

摘要： An input signal is routed to a first logic one reference signal generator or alternatively routed to a second logic one reference signal generator based at least one a voltage level of the input signal. When the voltage level of the input signal is less than a threshold value, the first logic one reference signal generator selectively generates a first logic one reference signal. When the voltage level of the input signal is greater than or equal to the threshold value, the second logic one reference signal generator alternatively generates a second logic one reference signal. The first and second logic one reference signals may be used to control a first voltage scaling circuit that drives a scaled output signal having a logic one value corresponding to the voltage level of the first logic one reference signal.

摘要翻译： 输入信号被路由到第一逻辑一个参考信号发生器，或者基于输入信号的至少一个电压电平路由到第二逻辑1参考信号发生器。 当输入信号的电压电平小于阈值时，第一逻辑1参考信号发生器选择性地产生第一逻辑1参考信号。 当输入信号的电压电平大于或等于阈值时，第二逻辑1参考信号发生器交替产生第二逻辑1参考信号。 第一和第二逻辑一个参考信号可以用于控制驱动具有对应于第一逻辑1参考信号的电压电平的逻辑1值的定标输出信号的第一电压缩放电路。

公开(公告)号：US07345510B1

公开(公告)日：2008-03-18

申请号：US11469311

申请日：2006-08-31

申请人： Oleg Drapkin ,  Grigori Temkine ,  Arvind Bomdica ,  Kevin Liang

发明人： Oleg Drapkin ,  Grigori Temkine ,  Arvind Bomdica ,  Kevin Liang

IPC分类号： H03K19/0175

CPC分类号： H03K19/0185 ,  H03K19/094

摘要： An input signal is routed to a first logic one reference signal generator or alternatively routed to a second logic one reference signal generator based at least one a voltage level of the input signal. When the voltage level of the input signal is less than a threshold value, the first logic one reference signal generator selectively generates a first logic one reference signal. When the voltage level of the input signal is greater than or equal to the threshold value, the second logic one reference signal generator alternatively generates a second logic one reference signal. The first and second logic one reference signals may be used to control a first voltage scaling circuit that drives a scaled output signal having a logic one value corresponding to the voltage level of the first logic one reference signal.

摘要翻译： 输入信号被路由到第一逻辑一个参考信号发生器，或者基于输入信号的至少一个电压电平路由到第二逻辑1参考信号发生器。 当输入信号的电压电平小于阈值时，第一逻辑1参考信号发生器选择性地产生第一逻辑1参考信号。 当输入信号的电压电平大于或等于阈值时，第二逻辑1参考信号发生器交替产生第二逻辑1参考信号。 第一和第二逻辑一个参考信号可以用于控制驱动具有对应于第一逻辑1参考信号的电压电平的逻辑1值的定标输出信号的第一电压缩放电路。

公开(公告)号：US07688925B2

公开(公告)日：2010-03-30

申请号：US11195082

申请日：2005-08-01

申请人： Edward Lee ,  Arvind Bomdica ,  Lin Chen ,  Claude Gauthier ,  Sam Huynh ,  Hiok-Tiaq Ng ,  John Ling ,  Jennifer Ho ,  Siji Menokki Kandiyil ,  Gin Yee ,  Joseph Macri

发明人： Edward Lee ,  Arvind Bomdica ,  Lin Chen ,  Claude Gauthier ,  Sam Huynh ,  Hiok-Tiaq Ng ,  John Ling ,  Jennifer Ho ,  Siji Menokki Kandiyil ,  Gin Yee ,  Joseph Macri

IPC分类号： H04L7/00

CPC分类号： H03L7/0814 ,  H03L7/07 ,  H03L7/0805 ,  H04L7/0004 ,  H04L7/0037 ,  H04L7/0337

摘要： An IO method and system for bit-deskewing are described. Embodiment includes a computer system with multiple components that transfer data among them. In one embodiment, a system component receives a forward strobe signal and multiple data bit signals from a transmitting component. The receiving component includes a forward strobe clock recovery circuit configurable to align a forward strobe sampling clock so as to improve sampling accuracy. The receiving component further includes at least one data bit clock recovery circuit configurable to align a data bit sampling clock so as to improve sampling accuracy, and to receive a signal from the forward strobe clock recovery circuit that causes the data bit sampling clock to track the forward strobe sampling clock during system operation.

摘要翻译： 描述了用于位移校正的IO方法和系统。 实施例包括具有在其间传送数据的多个组件的计算机系统。 在一个实施例中，系统组件从发送组件接收正向选通信号和多个数据位信号。 接收组件包括可选择对准前向选通采样时钟以提高采样精度的正向选通时钟恢复电路。 接收组件还包括至少一个数据比特时钟恢复电路，可配置为对准数据比特采样时钟，以提高采样精度，并接收来自正向选通时钟恢复电路的信号，使得数据比特采样时钟跟踪 系统运行期间的正向选通采样时钟。

公开(公告)号：US20080266009A1

公开(公告)日：2008-10-30

申请号：US11797081

申请日：2007-04-30

申请人： Kevin YiKai Liang ,  Arvind Bomdica ,  Min Xu ,  Ming So

发明人： Kevin YiKai Liang ,  Arvind Bomdica ,  Min Xu ,  Ming So

IPC分类号： H03B5/32

CPC分类号： H03B5/364 ,  H03B2200/0082

摘要： An ultra-low power crystal oscillator architecture that draws less than 2 μA during steady state operation. An amplifier stage is self biased and has input and output clamp circuits that limit its signal swing. Circuit values are selected such that there is sufficient transient load current for the first amplifier stage to oscillate, while at the same time the input and output clamp circuits maintain a sufficiently low swing of the stage such that the steady state average load current is on the order of less than 1 μA.

摘要翻译： 一种超低功耗晶体振荡器架构，在稳态运行期间吸收小于2μA。 放大器级是自偏置的，并具有限制其信号摆幅的输入和输出钳位电路。 选择电路值，使得第一放大器级有足够的瞬态负载电流进行振荡，同时输入和输出钳位电路保持级的足够低的摆幅，使得稳态平均负载电流在 小于1亩。

公开(公告)号：US07522010B2

公开(公告)日：2009-04-21

申请号：US11797081

申请日：2007-04-30

申请人： Kevin YiKai Liang ,  Arvind Bomdica ,  Min Xu ,  Ming So

发明人： Kevin YiKai Liang ,  Arvind Bomdica ,  Min Xu ,  Ming So

IPC分类号： H03C1/00

CPC分类号： H03B5/364 ,  H03B2200/0082

摘要： An ultra-low power crystal oscillator architecture that draws less than 2 μA during steady state operation. An amplifier stage is self biased and has input and output clamp circuits that limit its signal swing. Circuit values are selected such that there is sufficient transient load current for the first amplifier stage to oscillate, while at the same time the input and output clamp circuits maintain a sufficiently low swing of the stage such that the steady state average load current is on the order of less than 1 μA.

摘要翻译： 一种超低功耗晶体振荡器架构，在稳态运行期间吸收小于2μA。 放大器级是自偏置的，并具有限制其信号摆幅的输入和输出钳位电路。 选择电路值，使得第一放大器级有足够的瞬态负载电流进行振荡，同时输入和输出钳位电路保持级的足够低的摆幅，使得稳态平均负载电流在 小于1亩。

公开(公告)号：US20110148838A1

公开(公告)日：2011-06-23

申请号：US12640180

申请日：2009-12-17

申请人： Kevin Yikai Liang ,  Xin Liu ,  Arvind Bomdica ,  Ming-Ju Edward Lee

发明人： Kevin Yikai Liang ,  Xin Liu ,  Arvind Bomdica ,  Ming-Ju Edward Lee

IPC分类号： G06F3/038 ,  G05F1/10

CPC分类号： H03K19/018514 ,  H03K19/018528

摘要： A circuit includes a complementary current mode logic driver circuit and a dual feedback current mode logic bias circuit. The complementary current mode logic driver circuit provides a first output voltage and a second output voltage. The dual feedback current mode logic bias circuit includes a first feedback circuit and a second feedback circuit. The first feedback circuit provides a first bias voltage for the complementary current mode logic driver circuit in response to the first output voltage. The second feedback circuit provides a second bias voltage in response to the second output voltage.

摘要翻译： 电路包括互补电流模式逻辑驱动器电路和双反馈电流模式逻辑偏置电路。 互补电流模式逻辑驱动器电路提供第一输出电压和第二输出电压。 双反馈电流模式逻辑偏置电路包括第一反馈电路和第二反馈电路。 第一反馈电路响应于第一输出电压为互补电流模式逻辑驱动器电路提供第一偏置电压。 第二反馈电路响应于第二输出电压提供第二偏置电压。