公开(公告)号：US06818488B2

公开(公告)日：2004-11-16

申请号：US10332451

申请日：2003-09-08

申请人： Olivier Joubert ,  Giles Cunge ,  Johann Foucher ,  David Fuard ,  Marceline Bonvalot ,  Laurent Vallier

发明人： Olivier Joubert ,  Giles Cunge ,  Johann Foucher ,  David Fuard ,  Marceline Bonvalot ,  Laurent Vallier

IPC分类号： H01L21338

CPC分类号： H01L29/4958 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28114 ,  H01L29/42376

摘要： The invention relates to a process for making a gate for a CMOS transistor structure, made from a stack realized on a face in a semi-conducting material of a substrate, said stack comprising a gate isolation layer, a gate material layer and a gate mask in sequence, the process comprising the following steps: a) anisotropic etching of the top part of the gate material layer not masked by the gate mask, this etching step leaving the bottom part of the gate material layer and leading to the formation of a deposit composed of etching products on the etching sides resulting from the anisotropic etching, b) treatment of the deposit composed of etching products, to make a protection layer reinforced against subsequent etching of the gate material, c) etching of the bottom part of the gate material layer as far as the gate isolation layer, this etching comprising isotropic etching of the gate material layer to make the gate shorter at the bottom than at the top.

摘要翻译： 本发明涉及一种用于制造CMOS晶体管结构的栅极的方法，该栅极由在衬底的半导体材料的表面上实现的叠层制成，所述堆叠包括栅极隔离层，栅极材料层和栅极掩模 顺序地，该方法包括以下步骤：a）不被栅极掩模掩蔽的栅极材料层的顶部的各向异性蚀刻，该蚀刻步骤离开栅极材料层的底部并导致形成沉积物 由各向异性腐蚀产生的蚀刻侧面上的蚀刻产物组成，b）处理由蚀刻产物构成的沉积物，以形成对栅极材料的后续蚀刻加强的保护层，c）蚀刻栅极材料的底部 层，直到栅极隔离层，该蚀刻包括栅极材料层的各向同性蚀刻，以使栅极在底部比在顶部更短。

公开(公告)号：US06551698B1

公开(公告)日：2003-04-22

申请号：US09763532

申请日：2001-04-04

申请人： François Martin ,  Daniel Bensahel ,  Caroline Hernandez ,  Laurent Vallier

发明人： François Martin ,  Daniel Bensahel ,  Caroline Hernandez ,  Laurent Vallier

IPC分类号： C23G1602

CPC分类号： C23C28/044 ,  C23C8/28 ,  Y10T428/24926

摘要： Method for preparing a silicon substrate to form a thin electric insulating layer (24), characterized in that it comprises: a deoxidation step of at least one part of the silicon substrate (10), then a heat treatment step of the substrate at a temperature of 750° C. or less, the heat treatment being conducted in a NO-containing atmosphere at a pressure of 5.103 Pa (50 mBr) or less, in order to form a layer of silicon oxynitride (22) on the substrate. Use for the production of EPROM and DRAM memories.

摘要翻译： 一种制备硅衬底以形成薄电绝缘层（24）的方法，其特征在于，其包括：至少一部分硅衬底（10）的脱氧步骤，然后在基底的热处理步骤 750℃以下，在5.103Pa（50mBr）以下的压力下，在含NO气氛中进行热处理，以在基板上形成氮氧化硅层22。 用于生产EPROM和DRAM存储器。