公开(公告)号：US10936007B2

公开(公告)日：2021-03-02

申请号：US16374525

申请日：2019-04-03

Applicant: OmniVision Technologies, Inc.

Inventor： Li Yang ,  Qingle Wu ,  Zhixiang Jiang

IPC: G06F1/10 ,  G06F1/08 ,  G06F7/58 ,  H03K19/21

Abstract: A method for reducing a clock-data skew in a serial interface. A clock signal and a data signal are received through the serial interface at first and second inputs of an exclusive OR (XOR) averaging (XOR-averaging) gate. An output of the XOR-averaging gate is determined and compared with a target value. At least one of a delay of the clock signal and a delay of the data signal is determined based on comparing the output of the XOR-averaging gate with the target value. A skew between the clock signal and the data signal is reduced by delaying at least one of the clock signal and the data signal.

公开(公告)号：US20200319666A1

公开(公告)日：2020-10-08

申请号：US16374525

申请日：2019-04-03

Applicant: OmniVision Technologies, Inc.

Inventor： Li Yang ,  Qingle Wu ,  Zhixiang Jiang

IPC: G06F1/10 ,  G06F1/08 ,  G06F7/58 ,  H03K19/21

Abstract: A method for reducing a clock-data skew in a serial interface. A clock signal and a data signal are received through the serial interface at first and second inputs of an exclusive OR (XOR) averaging (XOR-averaging) gate. An output of the XOR-averaging gate is determined and compared with a target value. At least one of a delay of the clock signal and a delay of the data signal is determined based on comparing the output of the XOR-averaging gate with the target value. A skew between the clock signal and the data signal is reduced by delaying at least one of the clock signal and the data signal.