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公开(公告)号：US10312887B2
公开(公告)日：2019-06-04
申请号：US15365605
申请日：2016-11-30
Applicant: OmniVision Technologies, Inc.
Inventor： Li Yang , Charles Qingle Wu
Abstract: An integrated oscillator has an R-S flipflop; a first and second capacitor; a current source transistor; first and second current-steering transistors, each having a source coupled to the current source transistor, with drains coupled to the first and second capacitor respectively. The first current-steering transistor has gate coupled to a first output of the R-S flipflop, and the second current-steering transistor has gate coupled to a second output of the R-S flipflop. The oscillator has a first sense inverter having input from the first capacitor and powered by a feedback circuit adapted to sense voltages on the first and second capacitor; and a second sense inverter having input from the second capacitor and powered by the feedback circuit. The R-S flipflop has a first input coupled to an output of the first sense inverter and a second input coupled to an output of the second sense inverter.
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公开(公告)号：US10175715B2
公开(公告)日：2019-01-08
申请号：US15272145
申请日：2016-09-21
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Charles Qingle Wu , Li Yang , Zhenhua Zhu
Abstract: Apparatuses and methods for a reference clock-less CMOS image sensor are disclosed herein. An example apparatus may include a controller coupled to an image sensor via a serial bus, and the controller may provide an access burst to the image sensor over the serial bus, the access burst including a plurality of data signals and an associated clock signal, where the associated clock signal is a timing signal for the acquisition of bits of the plurality of data signals. The image sensor may calibrate an internal clock signal in response to a comparison of a number of cycles of the internal clock signal occurring during the access burst to a number of cycles of the associated clock signal occurring during the access burst, where the associated clock signal cycles at a first frequency and the internal clock signal cycles at a second frequency different than the first frequency.
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Patent Agency Ranking
公开(公告)号：US20180081389A1
公开(公告)日：2018-03-22
申请号：US15272145
申请日：2016-09-21
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Charles Qingle Wu , Li Yang , Zhenhua Zhu
CPC classification number: G06F1/08 , G06F3/005 , G06F13/4291 , H04N5/374
Abstract: Apparatuses and methods for a reference clock-less CMOS image sensor are disclosed herein. An example apparatus may include a controller coupled to an image sensor via a serial bus, and the controller may provide an access burst to the image sensor over the serial bus, the access burst including a plurality of data signals and an associated clock signal, where the associated clock signal is a timing signal for the acquisition of bits of the plurality of data signals. The image sensor may calibrate an internal clock signal in response to a comparison of a number of cycles of the internal clock signal occurring during the access burst to a number of cycles of the associated clock signal occurring during the access burst, where the associated clock signal cycles at a first frequency and the internal clock signal cycles at a second frequency different than the first frequency.
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4.发明授权公开(公告)号：US09900145B2
公开(公告)日：2018-02-20
申请号：US15159583
申请日：2016-05-19
Applicant: OmniVision Technologies, Inc.
Inventor： Li Yang , Wengen Wang , Charles Qingle Wu
CPC classification number: H04L7/0331 , G06F1/08 , H03K3/84 , H03K5/00 , H03K5/1252 , H03K5/131 , H03K5/133 , H03K5/14 , H03L7/16 , H04B1/69 , H04B15/02 , H04L5/005
Abstract: A spread-spectrum clock generator has a phase-locked loop locked to a reference signal that gives a stable-frequency output to a variable phase shifter. The variable phase shifter provides a spread-spectrum clock output because its phase-shift is determined by a pseudorandom sequence generator and the pseudorandom sequence generator changes its output regularly or irregularly within limits. The clock generator performs a method of generating a spread-spectrum clock including locking the phase-locked loop to the reference signal, and phase shifting the stable frequency signal by a phase-shift determined by the pseudorandom sequence generator; and changing the phase-shift determined by the pseudorandom sequence generator. Since phase shifting is performed open-loop, total phase shift is defined by design.
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公开(公告)号：US10936007B2
公开(公告)日：2021-03-02
申请号：US16374525
申请日：2019-04-03
Applicant: OmniVision Technologies, Inc.
Inventor： Li Yang , Qingle Wu , Zhixiang Jiang
Abstract: A method for reducing a clock-data skew in a serial interface. A clock signal and a data signal are received through the serial interface at first and second inputs of an exclusive OR (XOR) averaging (XOR-averaging) gate. An output of the XOR-averaging gate is determined and compared with a target value. At least one of a delay of the clock signal and a delay of the data signal is determined based on comparing the output of the XOR-averaging gate with the target value. A skew between the clock signal and the data signal is reduced by delaying at least one of the clock signal and the data signal.
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公开(公告)号：US11184196B1
公开(公告)日：2021-11-23
申请号：US17125605
申请日：2020-12-17
Applicant: OmniVision Technologies, Inc.
Inventor： Li Yang , Charles Qingle Wu , Nan Liu
Abstract: A digital differential line receiver includes a differential signal to single-ended conversion amplifier coupled to receive a data line and data-complement line of a differential signal; a first termination resistor coupled to the data line of the differential signal; a second termination resistor coupled to the data-complement line of the differential signal; a first impedance-adjusting transistor coupled between the first termination resistor and a common mode line; a second impedance-adjusting transistor coupled between the second termination resistor and the common mode line; a control-voltage generator coupled to sense the common mode line and provide a control voltage, the control voltage generator configured to adjust the control voltage to a voltage level such that a combined impedance of the first termination resistor, the first impedance-adjusting transistor, the second termination resistor, and the second impedance-adjusting transistor matches a specified impedance.
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公开(公告)号：US20200319666A1
公开(公告)日：2020-10-08
申请号：US16374525
申请日：2019-04-03
Applicant: OmniVision Technologies, Inc.
Inventor： Li Yang , Qingle Wu , Zhixiang Jiang
Abstract: A method for reducing a clock-data skew in a serial interface. A clock signal and a data signal are received through the serial interface at first and second inputs of an exclusive OR (XOR) averaging (XOR-averaging) gate. An output of the XOR-averaging gate is determined and compared with a target value. At least one of a delay of the clock signal and a delay of the data signal is determined based on comparing the output of the XOR-averaging gate with the target value. A skew between the clock signal and the data signal is reduced by delaying at least one of the clock signal and the data signal.
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