公开(公告)号：US20220129262A1

公开(公告)日：2022-04-28

申请号：US17427843

申请日：2020-02-20

Applicant: Optimum Semiconductor Technologies Inc.

Inventor： Mayan MOUDGILL ,  Pablo BALZOLA ,  Murugappan SENTHIVELAN ,  Vaidyanathan RAMDURAI ,  Sitij AGRAWAL

IPC: G06F9/30 ,  G06F7/544

Abstract: A system and an accelerator circuit including a register file comprising instruction registers to store an instruction for evaluating an elementary function, and data registers comprising a first data register to store an input value. The accelerator circuit further includes a successive cumulative rotation circuit comprising a reconfigurable inner stage to perform a successive cumulative rotation recurrence, and a determination circuit to determine a type of the elementary function based on the instruction, and responsive to determining that the input value is a fixed-point number, configure the reconfigurable inner stage to a configuration for evaluating the type of the elementary function, wherein the successive cumulative rotation circuit is to calculate an evaluation of the elementary function using the reconfigurable inner stage performing the successive cumulative rotation recurrence.

公开(公告)号：US20210319283A1

公开(公告)日：2021-10-14

申请号：US17351408

申请日：2021-06-18

Applicant: Optimum Semiconductor Technologies Inc.

Inventor： Mayan MOUDGILL ,  John GLOSSNER

IPC: G06N3/04 ,  G06F9/30 ,  G06F9/38

Abstract: A system includes a processor and an accelerator circuit including an input circuit block comprising an input processor to perform first tasks of the neural network application, a filter circuit block comprising a filter processor to perform second tasks of the neural network application, and a plurality of general-purpose filters communicatively coupled to the input circuit block, the filter circuit block, where the input circuit block and the filter circuit block form stages of an execution pipeline, a producer stage is to supply data values to a consumer stage, and operation of the consumer stage is on hold until a start flag stored in a first general-purpose register of the plurality of general-purpose registers to be set by the producer stage.

公开(公告)号：US20210311735A1

公开(公告)日：2021-10-07

申请号：US17266338

申请日：2019-08-13

Applicant: Optimum Semiconductor Technologies Inc.

Inventor： Mayan MOUDGILL ,  John GLOSSNER

IPC: G06F9/30 ,  G06F9/38

Abstract: A processor including a vector register file comprising a plurality of vector registers, at least one buffer register, and a vector processing core, communicatively connected to the vector register file and the at least one buffer register, to receive a vector instruction comprising a first identifier representing a first vector register of the plurality of vector registers, and a second identifier representing a second vector register of the plurality of vector registers, wherein the first vector register is a source register and the second vector register is a destination register, execute the vector instruction based on data values stored in the first vector register to generate a result and store the result in the at least one buffer register, and responsive to determining that the second vector register is safe to write, copy the result from the at least one buffer register to the second vector register.

公开(公告)号：US20230350688A1

公开(公告)日：2023-11-02

申请号：US18350729

申请日：2023-07-11

Applicant: Optimum Semiconductor Technologies Inc.

Inventor： Mayan MOUDGILL ,  John GLOSSNER

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3857 ,  G06F9/30101 ,  G06F9/3861 ,  G06F9/3869

Abstract: A processor includes a vector register file including vector registers, at least one buffer register, and a vector processing core to receive a vector instruction comprising a first identifier representing a first vector register of the vector registers, and a second identifier representing a second vector register of the vector registers, wherein the first vector register is a source register and the second vector register is a destination register, execute the vector instruction based on data values stored in the first vector register to generate a result and store the result in the at least one buffer register, and copy the result from the at least one buffer register to the second vector register.

公开(公告)号：US20220179653A1

公开(公告)日：2022-06-09

申请号：US17276598

申请日：2019-09-18

Applicant: Optimum Semiconductor Technologies Inc.

Inventor： Mayan MOUDGILL ,  Murugappan SENTHILVELAN

IPC: G06F9/30

Abstract: A processor includes a register file comprising a length register, a vector register file comprising a plurality of vector registers, a mask register file comprising a plurality of mask registers, and a vector instruction execution circuit to execute a masked vector instruction comprising a first length register identifier representing the length register, a first vector register identifier representing a first vector register of the vector register file, and a first mask register identifier representing a first mask register of the mask register file, wherein the length register is to store a length value representing a number of operations to be applied to data elements stored in the first vector register, the first mask register is to store a plurality of mask bits, and a first mask bit of the plurality of mask bits determines whether a corresponding first one of the operations causes an effect.

公开(公告)号：US20220137925A1

公开(公告)日：2022-05-05

申请号：US17427832

申请日：2020-02-20

Applicant: Optimum Semiconductor Technologies Inc.

Inventor： Mayan MOUDGILL ,  Pablo BALZOLA ,  Murugappan SENTHIVELAN ,  Vaidyanathan RAMDURAI ,  Sitij AGRAWAL

IPC: G06F7/548 ,  G06F17/17 ,  G06F7/544

Abstract: A system and an accelerator circuit including a register file comprising instruction registers to store a trigonometric calculation instruction for evaluating a trigonometric function, and data registers comprising a first data register to store a floating-point input value associated with the trigonometric calculation instruction. The accelerator circuit further includes a determination circuit to identify the trigonometric calculation function and the floating-point input value associated with the trigonometric calculation instruction and determine whether the floating-point input value is in a small value range, and an approximation circuit to responsive to determining that the floating-point input value is in the small value, receive the floating-point input value and calculate an approximation of the trigonometric function with respect to the input value.

公开(公告)号：US20220108148A1

公开(公告)日：2022-04-07

申请号：US17351425

申请日：2021-06-18

Applicant: Optimum Semiconductor Technologies Inc.

Inventor： Mayan MOUDGILL ,  John GLOSSNER

IPC: G06N3/04 ,  G06F9/30 ,  G06F9/38

Abstract: A system and an accelerator circuit includes an internal memory to store data received a memory associated with a processor and a filter circuit block comprising a plurality of circuit stripes, each circuit stripe including a filter processor, a plurality of filter circuits, and a slice of the internal memory assigned to the plurality of filter circuits, where the filter processor is to execute a filter instruction to read data values from the internal memory based on a first memory address, for each of the plurality of circuit stripes: load the data values in weight registers and input registers associated with the plurality of filter circuits of the circuit stripe to generate a plurality of filter results, and write a result generated using the plurality of filter circuits in the internal memory at a second memory address.

公开(公告)号：US20210319284A1

公开(公告)日：2021-10-14

申请号：US17351434

申请日：2021-06-18

Applicant: Optimum Semiconductor Technologies Inc.

Inventor： Mayan MOUDGILL ,  John GLOSSNER

IPC: G06N3/04 ,  G06F9/30 ,  G06F9/38

Abstract: A system and method include an accelerator circuit comprising an input circuit block, a filter circuit block, a post-processing circuit block, and an output circuit block and a processor to initialize the accelerator circuit, determining tasks of a neural network application to be performed by at least one of the input circuit block, the filter circuit block, the post-processing circuit block, or the output circuit block, assign each of the tasks to a corresponding one of the input circuit block, the filter circuit block, the post-processing circuit block, or the output circuit block, instruct the accelerator circuit to perform the tasks, and execute the neural network application based on results received from the accelerator circuit completing performance of the tasks.