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    System and architecture including processor and neural network accelerator
    1.
    发明授权
    System and architecture including processor and neural network accelerator 有权

    公开(公告)号：US12165030B2

    公开(公告)日：2024-12-10

    申请号：US17351434

    申请日：2021-06-18

    Applicant: Optimum Semiconductor Technologies Inc.

    Inventor： Mayan Moudgill ,  John Glossner

    IPC: G06N3/04 ,  G06F9/30 ,  G06F9/38 ,  G06F9/32 ,  G06F15/78

    Abstract: A system and method include an accelerator circuit comprising an input circuit block, a filter circuit block, a post-processing circuit block, and an output circuit block and a processor to initialize the accelerator circuit, determining tasks of a neural network application to be performed by at least one of the input circuit block, the filter circuit block, the post-processing circuit block, or the output circuit block, assign each of the tasks to a corresponding one of the input circuit block, the filter circuit block, the post-processing circuit block, or the output circuit block, instruct the accelerator circuit to perform the tasks, and execute the neural network application based on results received from the accelerator circuit completing performance of the tasks.

    DEVICE AND METHOD FOR CALCULATING ELEMENTARY FUNCTIONS USING SUCCESSIVE CUMULATIVE ROTATION CIRCUIT
    2.
    发明申请
    DEVICE AND METHOD FOR CALCULATING ELEMENTARY FUNCTIONS USING SUCCESSIVE CUMULATIVE ROTATION CIRCUIT 有权

    公开(公告)号：US20220129262A1

    公开(公告)日：2022-04-28

    申请号：US17427843

    申请日：2020-02-20

    Applicant: Optimum Semiconductor Technologies Inc.

    Inventor： Mayan MOUDGILL ,  Pablo BALZOLA ,  Murugappan SENTHIVELAN ,  Vaidyanathan RAMDURAI ,  Sitij AGRAWAL

    IPC: G06F9/30 ,  G06F7/544

    Abstract: A system and an accelerator circuit including a register file comprising instruction registers to store an instruction for evaluating an elementary function, and data registers comprising a first data register to store an input value. The accelerator circuit further includes a successive cumulative rotation circuit comprising a reconfigurable inner stage to perform a successive cumulative rotation recurrence, and a determination circuit to determine a type of the elementary function based on the instruction, and responsive to determining that the input value is a fixed-point number, configure the reconfigurable inner stage to a configuration for evaluating the type of the elementary function, wherein the successive cumulative rotation circuit is to calculate an evaluation of the elementary function using the reconfigurable inner stage performing the successive cumulative rotation recurrence.

    System and method to implement masked vector instructions
    7.
    发明授权
    System and method to implement masked vector instructions 有权

    公开(公告)号：US11650817B2

    公开(公告)日：2023-05-16

    申请号：US17276598

    申请日：2019-09-18

    Applicant: Optimum Semiconductor Technologies Inc.

    Inventor： Mayan Moudgill ,  Murugappan Senthilvelan

    IPC: G06F9/30

    CPC classification number: G06F9/30036 ,  G06F9/3013 ,  G06F9/30018

    Abstract: A processor includes a register file comprising a length register, a vector register file comprising a plurality of vector registers, a mask register file comprising a plurality of mask registers, and a vector instruction execution circuit to execute a masked vector instruction comprising a first length register identifier representing the length register, a first vector register identifier representing a first vector register of the vector register file, and a first mask register identifier representing a first mask register of the mask register file, wherein the length register is to store a length value representing a number of operations to be applied to data elements stored in the first vector register, the first mask register is to store a plurality of mask bits, and a first mask bit of the plurality of mask bits determines whether a corresponding first one of the operations causes an effect.

    DUAL ADAPTIVE COLLISION AVOIDANCE SYSTEM
    9.
    发明申请
    DUAL ADAPTIVE COLLISION AVOIDANCE SYSTEM 有权

    公开(公告)号：US20220063573A1

    公开(公告)日：2022-03-03

    申请号：US17275007

    申请日：2019-09-11

    Applicant: Optimum Semiconductor Technologies Inc.

    Inventor： Samantha MURPHY ,  John GLOSSNER ,  Sabin Daniel IANCU

    IPC: B60T7/22

    Abstract: An anti-collision system and method of a vehicle including a first sensor device to capture first sensor data associated with a first vehicle in front of the vehicle, a second sensor device to capture second sensor data associated with a second vehicle behind the vehicle, and a processing device to calculate, based on the first sensor data, a plurality of first parameters characterizing the first vehicle, calculate, based on the second sensor data, a plurality of second parameters characterizing the second vehicle, responsive to detecting a braking event by the first vehicle, determine, based on a rule taking into consideration at least one of the plurality of first parameters and at least one of the plurality of second parameters, a braking force for the vehicle, and generate a braking control signal that applies the braking force to brakes of the vehicle.

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