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    SYSTEM AND ARCHITECTURE INCLUDING PROCESSOR, ACCELERATOR AND THEIR OPERATIONS
    2.
    发明申请
    SYSTEM AND ARCHITECTURE INCLUDING PROCESSOR, ACCELERATOR AND THEIR OPERATIONS 有权

    公开(公告)号：US20210319283A1

    公开(公告)日：2021-10-14

    申请号：US17351408

    申请日：2021-06-18

    Applicant: Optimum Semiconductor Technologies Inc.

    Inventor： Mayan MOUDGILL ,  John GLOSSNER

    IPC: G06N3/04 ,  G06F9/30 ,  G06F9/38

    Abstract: A system includes a processor and an accelerator circuit including an input circuit block comprising an input processor to perform first tasks of the neural network application, a filter circuit block comprising a filter processor to perform second tasks of the neural network application, and a plurality of general-purpose filters communicatively coupled to the input circuit block, the filter circuit block, where the input circuit block and the filter circuit block form stages of an execution pipeline, a producer stage is to supply data values to a consumer stage, and operation of the consumer stage is on hold until a start flag stored in a first general-purpose register of the plurality of general-purpose registers to be set by the producer stage.

    VECTOR INSTRUCTION WITH PRECISE INTERRUPTS AND/OR OVERWRITES
    3.
    发明申请
    VECTOR INSTRUCTION WITH PRECISE INTERRUPTS AND/OR OVERWRITES 有权

    公开(公告)号：US20210311735A1

    公开(公告)日：2021-10-07

    申请号：US17266338

    申请日：2019-08-13

    Applicant: Optimum Semiconductor Technologies Inc.

    Inventor： Mayan MOUDGILL ,  John GLOSSNER

    IPC: G06F9/30 ,  G06F9/38

    Abstract: A processor including a vector register file comprising a plurality of vector registers, at least one buffer register, and a vector processing core, communicatively connected to the vector register file and the at least one buffer register, to receive a vector instruction comprising a first identifier representing a first vector register of the plurality of vector registers, and a second identifier representing a second vector register of the plurality of vector registers, wherein the first vector register is a source register and the second vector register is a destination register, execute the vector instruction based on data values stored in the first vector register to generate a result and store the result in the at least one buffer register, and responsive to determining that the second vector register is safe to write, copy the result from the at least one buffer register to the second vector register.

    DUAL ADAPTIVE COLLISION AVOIDANCE SYSTEM
    5.
    发明申请
    DUAL ADAPTIVE COLLISION AVOIDANCE SYSTEM 有权

    公开(公告)号：US20220063573A1

    公开(公告)日：2022-03-03

    申请号：US17275007

    申请日：2019-09-11

    Applicant: Optimum Semiconductor Technologies Inc.

    Inventor： Samantha MURPHY ,  John GLOSSNER ,  Sabin Daniel IANCU

    IPC: B60T7/22

    Abstract: An anti-collision system and method of a vehicle including a first sensor device to capture first sensor data associated with a first vehicle in front of the vehicle, a second sensor device to capture second sensor data associated with a second vehicle behind the vehicle, and a processing device to calculate, based on the first sensor data, a plurality of first parameters characterizing the first vehicle, calculate, based on the second sensor data, a plurality of second parameters characterizing the second vehicle, responsive to detecting a braking event by the first vehicle, determine, based on a rule taking into consideration at least one of the plurality of first parameters and at least one of the plurality of second parameters, a braking force for the vehicle, and generate a braking control signal that applies the braking force to brakes of the vehicle.

    FEEDBACKWARD DECODER FOR PARAMETER EFFICIENT SEMANTIC IMAGE SEGMENTATION
    7.
    发明申请
    FEEDBACKWARD DECODER FOR PARAMETER EFFICIENT SEMANTIC IMAGE SEGMENTATION 有权

    公开(公告)号：US20220262002A1

    公开(公告)日：2022-08-18

    申请号：US17623714

    申请日：2020-06-30

    Applicant: Optimum Semiconductor Technologies Inc.

    Inventor： Beinan WANG ,  John GLOSSNER ,  Sabin Daniel IANCU

    IPC: G06T7/10 ,  G06T3/40

    Abstract: A system and method relating to constructing an encoder and decoder neural network for providing semantic image segmentation includes generating an encoder comprising encoding convolution layers, each of the encoding convolution layers specifying an encoding filter operation using a respective first filter kernel, generating a decoder corresponding to the encoder, the decoder comprising decoding convolution layers, each of the decoding convolution layers being associated with a corresponding encoding convolution layer, and each of the decoding convolution layers specifying a decoding filter operation using a respective second filter kernel derived from the first filter kernel of the corresponding encoder convolution layer, and providing an input image to the encoder and the decoder for semantic image segmentation.

    VECTOR INSTRUCTION WITH PRECISE INTERRUPTS AND/OR OVERWRITES
    9.
    发明公开
    VECTOR INSTRUCTION WITH PRECISE INTERRUPTS AND/OR OVERWRITES 审中-公开

    公开(公告)号：US20230350688A1

    公开(公告)日：2023-11-02

    申请号：US18350729

    申请日：2023-07-11

    Applicant: Optimum Semiconductor Technologies Inc.

    Inventor： Mayan MOUDGILL ,  John GLOSSNER

    IPC: G06F9/38 ,  G06F9/30

    CPC classification number: G06F9/3857 ,  G06F9/30101 ,  G06F9/3861 ,  G06F9/3869

    Abstract: A processor includes a vector register file including vector registers, at least one buffer register, and a vector processing core to receive a vector instruction comprising a first identifier representing a first vector register of the vector registers, and a second identifier representing a second vector register of the vector registers, wherein the first vector register is a source register and the second vector register is a destination register, execute the vector instruction based on data values stored in the first vector register to generate a result and store the result in the at least one buffer register, and copy the result from the at least one buffer register to the second vector register.

    SYSTEM AND ARCHITECTURE NEURAL NETWORK ACCELERATOR INCLUDING FILTER CIRCUIT
    10.
    发明申请
    SYSTEM AND ARCHITECTURE NEURAL NETWORK ACCELERATOR INCLUDING FILTER CIRCUIT 有权

    公开(公告)号：US20220108148A1

    公开(公告)日：2022-04-07

    申请号：US17351425

    申请日：2021-06-18

    Applicant: Optimum Semiconductor Technologies Inc.

    Inventor： Mayan MOUDGILL ,  John GLOSSNER

    IPC: G06N3/04 ,  G06F9/30 ,  G06F9/38

    Abstract: A system and an accelerator circuit includes an internal memory to store data received a memory associated with a processor and a filter circuit block comprising a plurality of circuit stripes, each circuit stripe including a filter processor, a plurality of filter circuits, and a slice of the internal memory assigned to the plurality of filter circuits, where the filter processor is to execute a filter instruction to read data values from the internal memory based on a first memory address, for each of the plurality of circuit stripes: load the data values in weight registers and input registers associated with the plurality of filter circuits of the circuit stripe to generate a plurality of filter results, and write a result generated using the plurality of filter circuits in the internal memory at a second memory address.

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