公开(公告)号：US09275175B2

公开(公告)日：2016-03-01

申请号：US14179127

申请日：2014-02-12

Applicant: Oracle International Corporation

Inventor： Amit Agarwal ,  Alexander Korobkov

IPC: G06F17/50

CPC classification number: G06F17/5022 ,  G06F17/5045 ,  G06F2217/62 ,  G06F2217/74

Abstract: A system that visualizes a clock tree for an integrated circuit receives an extracted cell library, an extracted clock netlist including clock headers and interconnects, and simulation results. The system generates an internal data structure for the clock headers, and divides the clock headers into a plurality of levels based on the interconnects. The system then orders the clock headers from a lowest level to a highest level, and displays the ordered clock headers in an untangled manner.

Abstract translation: 可视化集成电路的时钟树的系统接收提取的单元库，提取的时钟网表，包括时钟标题和互连以及模拟结果。 该系统产生用于时钟标头的内部数据结构，并且基于互连将时钟标头划分成多个级别。 系统然后将时钟标头从最低级别排列到最高级别，并以无凸起的方式显示有序的时钟标头。

公开(公告)号：US09836562B2

公开(公告)日：2017-12-05

申请号：US14814757

申请日：2015-07-31

Applicant: Oracle International Corporation

Inventor： Qing He ,  Wai Chung William Au ,  Alexander Korobkov

IPC: G06F17/50

CPC classification number: G06F17/5009 ,  G06F17/5036 ,  G06F17/5068 ,  G06F17/5081

Abstract: A method for modeling electrostatic discharges. The method may include obtaining a circuit netlist for an integrated circuit. The circuit netlist may describe connection information for various electronic components within the integrated circuit. The method may further include obtaining, by removing a portion of the electronic components from the circuit netlist, a reduced netlist. The method may further include determining, using the reduced netlist, various circuit parameters regarding an electrostatic discharge event for the integrated circuit. The method may further include simulating, using the circuit parameters, a discharge path within the integrated circuit for the electrostatic discharge event.

公开(公告)号：US20150339419A1

公开(公告)日：2015-11-26

申请号：US14285471

申请日：2014-05-22

Applicant: Oracle International Corporation

Inventor： Alexander Korobkov ,  Subramanian Venkateswaran ,  Wai Chung William Au

IPC: G06F17/50

CPC classification number: G06F17/5036

Abstract: A method for calculating voltage values in a power grid, including: obtaining a primary circuit representation (PCR) corresponding to the power grid and including: multiple nodes separated by multiple impedances; and an independent source connected to one node; identifying a high degree node; obtaining a modified circuit representation (MCR) by connecting, in the PCR, an auxiliary voltage source having an auxiliary voltage value to the high degree node, the MCR including a modified characteristic matrix and a modified source vector; calculating a modified state vector based on the modified characteristic matrix and the modified source vector; generating an admittance matrix based on the multiple impedances and the auxiliary voltage; obtaining an auxiliary voltage adjustment value using the admittance matrix; obtaining a primary state vector by adjusting the modified state vector using the admittance matrix and the auxiliary voltage adjustment value; and obtaining the voltage values from the primary state vector.

Abstract translation: 一种用于计算电网中的电压值的方法，包括：获得对应于电网的主电路表示（PCR），并包括：由多个阻抗分隔的多个节点; 和连接到一个节点的独立源; 识别高度节点; 通过在PCR中连接具有辅助电压值的辅助电压源到高度节点来获得修改的电路表示（MCR），MCR包括修改的特征矩阵和修改的源向量; 基于修改的特征矩阵和修改的源向量计算修改的状态向量; 基于多个阻抗和辅助电压产生导纳矩阵; 使用导纳矩阵获得辅助电压调整值; 通过使用导纳矩阵和辅助电压调整值调整修正状态矢量来获得主状态矢量; 并从主状态矢量获得电压值。