公开(公告)号：US09136850B2

公开(公告)日：2015-09-15

申请号：US14146883

申请日：2014-01-03

Applicant: Oracle International Corporation

Inventor： Robert P. Masleid ,  Anand Dixit

IPC: H03L7/00 ,  H03K5/14

CPC classification number: H03L7/00 ,  H03K5/14

Abstract: A phase alignment circuit is disclosed. In one embodiment, the circuit includes a register configured to capture and store, in parallel from a delay unit, a plurality of samples of a first signal, responsive to a change of state of a second signal. The circuit further includes a detection circuit configured to detect a bit position in the register at which a state change of the first signal occurs based on a concurrent evaluation of all samples of the first signal. Selection circuitry in the phase alignment circuit is configured to select an output from a one of a plurality of delay elements of the delay unit based on in the bit position at which the state change was detected. The selection circuitry is configured to output a third signal that is a delayed version of the first signal.

Abstract translation: 公开了一种相位对准电路。 在一个实施例中，电路包括寄存器，其被配置为响应于第二信号的状态改变而从延迟单元并行存储和存储第一信号的多个样本。 该电路还包括检测电路，该检测电路被配置为基于对第一信号的所有采样的并发评估来检测在第一信号的状态变化发生的寄存器中的位位置。 相位对准电路中的选择电路被配置为基于在检测到状态改变的位位置中选择来自延迟单元的多个延迟元件中的一个的输出。 选择电路被配置为输出作为第一信号的延迟版本的第三信号。

公开(公告)号：US20150194968A1

公开(公告)日：2015-07-09

申请号：US14146883

申请日：2014-01-03

Applicant: ORACLE INTERNATIONAL CORPORATION

Inventor： Robert P. Masleid ,  Anand Dixit

IPC: H03L7/00 ,  H03K5/14

CPC classification number: H03L7/00 ,  H03K5/14

Abstract: A phase alignment circuit is disclosed. In one embodiment, the circuit includes a register configured to capture and store, in parallel from a delay unit, a plurality of samples of a first signal, responsive to a change of state of a second signal. The circuit further includes a detection circuit configured to detect a bit position in the register at which a state change of the first signal occurs based on a concurrent evaluation of all samples of the first signal. Selection circuitry in the phase alignment circuit is configured to select an output from a one of a plurality of delay elements of the delay unit based on in the bit position at which the state change was detected. The selection circuitry is configured to output a third signal that is a delayed version of the first signal.

Abstract translation: 公开了一种相位对准电路。 在一个实施例中，电路包括寄存器，其被配置为响应于第二信号的状态改变而从延迟单元并行存储和存储第一信号的多个样本。 该电路还包括检测电路，该检测电路被配置为基于对第一信号的所有采样的并发评估来检测在第一信号的状态变化发生的寄存器中的位位置。 相位对准电路中的选择电路被配置为基于在检测到状态改变的位位置中选择来自延迟单元的多个延迟元件中的一个的输出。 选择电路被配置为输出作为第一信号的延迟版本的第三信号。