公开(公告)号：US10193569B2

公开(公告)日：2019-01-29

申请号：US14477867

申请日：2014-09-05

申请人： PHISON ELECTRONICS CORP.

发明人： Chien-Fu Tseng ,  Tsai-Cheng Lin ,  Yen-Chiao Lai

IPC分类号： H03M13/11 ,  H04L1/00 ,  H03M13/25 ,  G06F11/07 ,  H03M13/37 ,  H03M13/29

摘要： A decoding method, a memory storage device and a memory control circuit unit are provided. The decoding method includes: executing at least one first iteration decoding procedure of an LDPC on a first codeword according to a first clock signal by a correcting circuit; generating a control parameter according to a first iteration count of the first iteration decoding procedure; outputting a second clock signal to the correcting circuit according to the control parameter; and executing at least one second iteration decoding procedure of the LDPC on a second codeword according to the second clock signal by the correcting circuit.

公开(公告)号：US20150358036A1

公开(公告)日：2015-12-10

申请号：US14475585

申请日：2014-09-03

申请人： PHISON ELECTRONICS CORP.

发明人： Chien-Fu Tseng

IPC分类号： H03M13/29

CPC分类号： H03M13/1108 ,  G06F11/1012 ,  H03M13/1102 ,  H03M13/1128 ,  H03M13/1171 ,  H03M13/2957 ,  H03M13/3746

摘要： A decoding method, a memory storage device and a memory control circuit unit are provided. The decoding method includes: sending a read command sequence for reading multiple memory cells so as to obtain multiple first bits; determining whether the first bits have a first error; if the first bits have the first error, executing a first iteration decoding procedure on the first bits so as to obtain multiple second bits, and recording first bit flipping information of the first iteration decoding procedure; determining whether the second bits have a second error; and If the second bits have the at least one second error, executing a second iteration decoding procedure on the second bits according to the first bit flipping information so as to obtain multiple third bits.

摘要翻译： 提供了解码方法，存储器存储装置和存储器控制电路单元。 解码方法包括：发送用于读取多个存储器单元的读命令序列，以获得多个第一位; 确定所述第一比特是否具有第一误差; 如果第一比特具有第一错误，则对第一比特执行第一迭代解码过程以获得多个第二比特，并记录第一迭代解码过程的第一比特翻转信息; 确定所述第二比特是否具有第二误差; 并且如果第二比特具有至少一个第二错误，则根据第一比特翻转信息对第二比特执行第二迭代解码过程，以获得多个第三比特。

公开(公告)号：US09362951B2

公开(公告)日：2016-06-07

申请号：US14145989

申请日：2014-01-01

申请人： PHISON ELECTRONICS CORP.

发明人： Chien-Fu Tseng

IPC分类号： G11C29/00 ,  H03M13/11 ,  G06F11/10

CPC分类号： H03M13/1105 ,  G06F11/1012 ,  H03M13/1108 ,  H03M13/1111 ,  H03M13/1117

摘要： A decoding method, a memory storage device, a memory controlling circuit unit and a decoding circuit for low density parity code (LDPC) are provided. The decoding method includes: reading a data bit of each memory cell; performing a parity check procedure on the data bits to generate a plurality of checks; in an iterative decoding of LDPC, obtaining a reliability message of each data bit according to the checks and deciding an index of an error bit from the data bits according to the reliability messages; determining whether the index of the error bit and the checks comply with a parity criteria; and if the index of the error bit and the checks comply with the parity criteria, stopping the iterative decoding and outputting the index of the error bit. Accordingly, a decoding latency is decreased.

摘要翻译： 提供了解码方法，存储器存储装置，存储器控制电路单元和用于低密度奇偶校验码（LDPC）的解码电路。 解码方法包括：读取每个存储单元的数据位; 对数据位执行奇偶校验程序以产生多个检查; 在LDPC的迭代解码中，根据可靠性消息，根据检查并根据数据比特确定错误比特的索引，获得每个数据比特的可靠性消息; 确定错误位的索引和检查是否符合奇偶校验标准; 并且如果错误位的索引和检查符合奇偶校验标准，则停止迭代解码并输出错误位的索引。 因此，解码等待时间减少。

公开(公告)号：US20150169401A1

公开(公告)日：2015-06-18

申请号：US14264040

申请日：2014-04-28

申请人： PHISON ELECTRONICS CORP.

发明人： Chien-Fu Tseng

IPC分类号： G06F11/10

CPC分类号： G06F11/1068 ,  G06F11/1048

摘要： A decoding method, a memory storage device and a memory controlling circuit unit are provided. First, memory cells are read to obtain verification bits. A first hard bit mode decoding procedure is performed according to the verification bits and whether the first hard bit mode decoding procedure generates a first valid codeword is determined by a first correcting circuit. If the first valid codeword is generated, the first valid codeword is outputted. If the first valid codeword is not generated, a second hard bit mode decoding procedure is performed, and whether the second hard bit mode decoding procedure generates a second valid codeword is determined by a second correcting circuit. A precision of the first correcting circuit is less than a precision of the second correcting circuit. Accordingly, the speed of decoding is increased.

摘要翻译： 提供了解码方法，存储器存储装置和存储器控制电路单元。 首先，读取存储单元以获得验证位。 根据验证位执行第一硬比特模式解码过程，以及由第一校正电路确定第一硬比特模式解码过程是否产生第一有效码字。 如果产生第一有效码字，则输出第一有效码字。 如果不产生第一有效码字，则执行第二硬比特模式解码过程，并且由第二校正电路确定第二硬比特模式解码过程是否产生第二有效码字。 第一校正电路的精度小于第二校正电路的精度。 因此，解码速度提高。

公开(公告)号：US20150113353A1

公开(公告)日：2015-04-23

申请号：US14145989

申请日：2014-01-01

申请人： PHISON ELECTRONICS CORP.

发明人： Chien-Fu Tseng

IPC分类号： H03M13/11 ,  G06F11/10

CPC分类号： H03M13/1105 ,  G06F11/1012 ,  H03M13/1108 ,  H03M13/1111 ,  H03M13/1117

摘要： A decoding method, a memory storage device, a memory controlling circuit unit and a decoding circuit for low density parity code (LDPC) are provided. The decoding method includes: reading a data bit of each memory cell; performing a parity check procedure on the data bits to generate a plurality of checks; in an iterative decoding of LDPC, obtaining a reliability message of each data bit according to the checks and deciding an index of an error bit from the data bits according to the reliability messages; determining whether the index of the error bit and the checks comply with a parity criteria; and if the index of the error bit and the checks comply with the parity criteria, stopping the iterative decoding and outputting the index of the error bit. Accordingly, a decoding latency is decreased.

摘要翻译： 提供了解码方法，存储器存储装置，存储器控制电路单元和用于低密度奇偶校验码（LDPC）的解码电路。 解码方法包括：读取每个存储单元的数据位; 对数据位执行奇偶校验程序以产生多个检查; 在LDPC的迭代解码中，根据可靠性消息，根据检查并根据数据比特确定错误比特的索引，获得每个数据比特的可靠性消息; 确定错误位的索引和检查是否符合奇偶校验标准; 并且如果错误位的索引和检查符合奇偶校验标准，则停止迭代解码并输出错误位的索引。 因此，解码等待时间减少。

公开(公告)号：US09543983B2

公开(公告)日：2017-01-10

申请号：US14475585

申请日：2014-09-03

申请人： PHISON ELECTRONICS CORP.

发明人： Chien-Fu Tseng

IPC分类号： G06F11/10 ,  H03M13/11 ,  H03M13/29 ,  H03M13/37

CPC分类号： H03M13/1108 ,  G06F11/1012 ,  H03M13/1102 ,  H03M13/1128 ,  H03M13/1171 ,  H03M13/2957 ,  H03M13/3746

摘要： A decoding method, a memory storage device and a memory control circuit unit are provided. The decoding method includes: sending a read command sequence for reading multiple memory cells so as to obtain multiple first bits; determining whether the first bits have a first error; if the first bits have the first error, executing a first iteration decoding procedure on the first bits so as to obtain multiple second bits, and recording first bit flipping information of the first iteration decoding procedure; determining whether the second bits have a second error; and If the second bits have the at least one second error, executing a second iteration decoding procedure on the second bits according to the first bit flipping information so as to obtain multiple third bits.

摘要翻译： 提供了解码方法，存储器存储装置和存储器控制电路单元。 解码方法包括：发送用于读取多个存储器单元的读命令序列，以获得多个第一位; 确定所述第一比特是否具有第一误差; 如果第一比特具有第一错误，则对第一比特执行第一迭代解码过程以获得多个第二比特，并记录第一迭代解码过程的第一比特翻转信息; 确定所述第二比特是否具有第二误差; 并且如果第二比特具有至少一个第二错误，则根据第一比特翻转信息对第二比特执行第二迭代解码过程，以获得多个第三比特。

公开(公告)号：US09342404B2

公开(公告)日：2016-05-17

申请号：US14264040

申请日：2014-04-28

申请人： PHISON ELECTRONICS CORP.

发明人： Chien-Fu Tseng

IPC分类号： H04L1/00 ,  G06F11/10

CPC分类号： G06F11/1068 ,  G06F11/1048

摘要： A decoding method, a memory storage device and a memory controlling circuit unit are provided. First, memory cells are read to obtain verification bits. A first hard bit mode decoding procedure is performed according to the verification bits and whether the first hard bit mode decoding procedure generates a first valid codeword is determined by a first correcting circuit. If the first valid codeword is generated, the first valid codeword is outputted. If the first valid codeword is not generated, a second hard bit mode decoding procedure is performed, and whether the second hard bit mode decoding procedure generates a second valid codeword is determined by a second correcting circuit. A precision of the first correcting circuit is less than a precision of the second correcting circuit. Accordingly, the speed of decoding is increased.

摘要翻译： 提供了解码方法，存储器存储装置和存储器控制电路单元。 首先，读取存储单元以获得验证位。 根据验证位执行第一硬比特模式解码过程，以及由第一校正电路确定第一硬比特模式解码过程是否产生第一有效码字。 如果产生第一有效码字，则输出第一有效码字。 如果不产生第一有效码字，则执行第二硬比特模式解码过程，并且由第二校正电路确定第二硬比特模式解码过程是否产生第二有效码字。 第一校正电路的精度小于第二校正电路的精度。 因此，解码速度提高。

公开(公告)号：US20160020784A1

公开(公告)日：2016-01-21

申请号：US14477867

申请日：2014-09-05

申请人： PHISON ELECTRONICS CORP.

发明人： Chien-Fu Tseng ,  Tsai-Cheng Lin ,  Yen-Chiao Lai

IPC分类号： H03M13/11

CPC分类号： H03M13/1128 ,  G06F11/076 ,  H03M13/255 ,  H03M13/2948 ,  H03M13/3707 ,  H03M13/3746 ,  H03M13/3753 ,  H04L1/005

摘要： A decoding method, a memory storage device and a memory control circuit unit are provided. The decoding method includes: executing at least one first iteration decoding procedure of an LDPC on a first codeword according to a first clock signal by a correcting circuit; generating a control parameter according to a first iteration count of the first iteration decoding procedure; outputting a second clock signal to the correcting circuit according to the control parameter; and executing at least one second iteration decoding procedure of the LDPC on a second codeword according to the second clock signal by the correcting circuit.

摘要翻译： 提供了解码方法，存储器存储装置和存储器控制电路单元。 解码方法包括：通过校正电路根据第一时钟信号在第一码字上执行LDPC的至少一个第一迭代解码过程; 根据所述第一迭代解码过程的第一迭代次数生成控制参数; 根据所述控制参数向所述校正电路输出第二时钟信号; 以及通过所述校正电路根据所述第二时钟信号在第二码字上执行所述LDPC的至少一个第二迭代解码过程。