公开(公告)号：US12112808B2

公开(公告)日：2024-10-08

申请号：US18179372

申请日：2023-03-07

申请人： PHISON ELECTRONICS CORP.

发明人： Szu-Wei Chen ,  An-Cin Li ,  Yu-Hung Lin ,  Kai-Wei Tsou

IPC分类号： G06F11/10 ,  G06F3/06 ,  G06F11/07 ,  G06F11/30 ,  G06F13/16 ,  G06F13/28 ,  G11C16/04 ,  G11C16/26

CPC分类号： G11C16/26 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0688 ,  G06F11/1068 ,  G11C16/0483

摘要： A read voltage calibration method, a memory storage device, and a memory control circuit unit are provided. The read voltage calibration method includes: reading data from a first physical unit by using multiple read voltage levels; decoding the data to obtain multiple error evaluation parameters; determining a first vector distance parameter according to a first error evaluation parameter; determining multiple candidate read voltage levels according to the first vector distance parameter and a first read voltage level; determining a target read voltage level according to one of the candidate read voltage levels; and reading the data again from the first physical unit by using the target read voltage level.

公开(公告)号：US20240249778A1

公开(公告)日：2024-07-25

申请号：US18179372

申请日：2023-03-07

申请人： PHISON ELECTRONICS CORP.

发明人： Szu-Wei Chen ,  An-Cin Li ,  Yu-Hung Lin ,  Kai-Wei Tsou

IPC分类号： G11C16/26 ,  G06F3/06 ,  G06F11/10 ,  G11C16/04

CPC分类号： G11C16/26 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0688 ,  G06F11/1068 ,  G11C16/0483

摘要： A read voltage calibration method, a memory storage device, and a memory control circuit unit are provided. The read voltage calibration method includes: reading data from a first physical unit by using multiple read voltage levels; decoding the data to obtain multiple error evaluation parameters; determining a first vector distance parameter according to a first error evaluation parameter; determining multiple candidate read voltage levels according to the first vector distance parameter and a first read voltage level; determining a target read voltage level according to one of the candidate read voltage levels; and reading the data again from the first physical unit by using the target read voltage level.

公开(公告)号：US20230037782A1

公开(公告)日：2023-02-09

申请号：US17460274

申请日：2021-08-29

申请人： PHISON ELECTRONICS CORP.

发明人： Yi-Hsiang MA ,  Szu-Wei Chen ,  Yu-Hung Lin ,  An-Cheng Liu

IPC分类号： G06N3/08 ,  G06N3/04 ,  G06K9/62 ,  G06T5/50

摘要： A method for training an asymmetric generative adversarial network to generate an image and an electronic apparatus using the same are provided. The method includes the following. A first real image belonging to a first category, a second real image belonging to a second category and a third real image belonging to a third category are input to an asymmetric generative adversarial network for training the asymmetric generative adversarial network, and the asymmetric generative adversarial network includes a first generator, a second generator, a first discriminator and a second discriminator. A fourth real image belonging to the second category is input to the first generator in the trained asymmetric generative adversarial network to generate a defect image.