公开(公告)号：US20250104787A1

公开(公告)日：2025-03-27

申请号：US18885111

申请日：2024-09-13

Applicant: POSTECH RESEARCH AND BUSINESS DEVELOPMENT FOUNDATION

Inventor： Seyoung KIM ,  Byoungwoo LEE ,  Jeonghoon SON ,  Seungkun KIM

IPC: G11C27/00 ,  G06N3/065 ,  H10B63/00 ,  H10N70/20

Abstract: The present disclosure relates to a three-terminal synaptic device for artificial neural network learning, a synaptic array using the same, and a method of operating the same. The three-terminal synaptic device includes a first transistor; an electrochemical memory (ECRAM) connected in parallel to the first transistor; and a second transistor connected in series to the parallel structure. Accordingly, the present disclosure can achieve an accuracy improvement of inference and learning operations in an artificial neural network through parallel operation by configuring a cross-point array based on the synaptic device with the three-terminal structure comprised of the electrochemical memory and two transistors.

公开(公告)号：US20250077855A1

公开(公告)日：2025-03-06

申请号：US18817862

申请日：2024-08-28

Applicant: POSTECH RESEARCH AND BUSINESS DEVELOPMENT FOUNDATION

Inventor： Seyoung KIM ,  Seungkun KIM ,  Jeonghoon SON

IPC: G06N3/065 ,  G11C11/54 ,  H10N70/00 ,  H10N70/20

Abstract: The present disclosure relates to a double gate neuromorphic memory device and a manufacturing method thereof. The double gate neuromorphic memory device is an electrochemical device, and includes a bottom gate provided on an upper portion of a semiconductor substrate, a channel area surrounding the upper portion and side surfaces of the bottom gate, a source electrode and a drain electrode provided in contact with both sides of the channel area, and a top gate provided on an upper portion of a channel area between the source electrode and the drain electrode.

公开(公告)号：US20230047277A1

公开(公告)日：2023-02-16

申请号：US17871855

申请日：2022-07-22

Applicant: POSTECH Research and Business Development Foundation

Inventor： Seyoung KIM ,  Doyoon KIM ,  Hyunjeong KWAK ,  Jeonghoon SON ,  Chuljun LEE

IPC: H01L45/00 ,  H01L27/24 ,  G06N3/04

Abstract: Provided is a three-dimensional vertical memory device including: a semiconductor substrate, a vertical columnar channel region provided on the semiconductor substrate and having a void of a predetermined size therein; a source electrode and a drain electrode spaced apart from each other with the channel region interposed therebetween; and a gate stack formed on the channel region.