公开(公告)号：US20030059996A1

公开(公告)日：2003-03-27

申请号：US10060590

申请日：2002-01-30

Applicant: ProMos Technologies Inc.

Inventor： Nien-Yu Tsai ,  Yung-Ching Wang

IPC: H01L021/8238

CPC classification number: H01L21/76897 ,  H01L21/28247 ,  H01L21/823425 ,  H01L21/823475

Abstract: A method for forming a gate structure is provided. The forming method includes steps of providing a semiconductor substrate; forming an insulation layer, a first gate conductor layer, a second gate conductor layer, and a masking layer on the semiconductor substrate; removing portions of the masking layer, the semiconductor substrate, and the first gate conductor layer to define the gate structure by etching; executing a cleaning process to the semiconductor with a specific cleaning agent for etching the second gate conductor layer, thereby removing portions of the second gate conductor layer in the gate structure; and performing a thermal treatment process to the semiconductor substrate and forming an insulation spacer on the side surface of the gate structure.

Abstract translation: 提供一种形成栅极结构的方法。 成形方法包括提供半导体衬底的步骤; 在半导体衬底上形成绝缘层，第一栅极导体层，第二栅极导体层和掩模层; 去除掩模层，半导体衬底和第一栅极导体层的部分，以通过蚀刻限定栅极结构; 利用用于蚀刻第二栅极导体层的特定清洁剂对半导体执行清洁处理，从而去除栅极结构中的第二栅极导体层的部分; 对所述半导体基板进行热处理，在所述栅极结构的侧面形成绝缘间隔物。

公开(公告)号：US20040067654A1

公开(公告)日：2004-04-08

申请号：US10265826

申请日：2002-10-07

Applicant: PROMOS TECHNOLOGIES, INC.

Inventor： Chun-Wei Chen ,  Hong-Long Chang ,  Nien-Yu Tsai

IPC: H01L021/302 ,  H01L021/461

CPC classification number: H01L21/3065

Abstract: The present invention relates to a method of reducing needle-like defects generated on a wafer rim in an etching process, wherein the etching process using both a photoresist material and hardmask material as a mask. After removing the photoresist material and the hardmask material, said method comprising the steps of: (i) depositing the photoresist material on the wafer again; (ii) performing wafer edge exposure (WEE) to form a ring of the wafer edge; and (iii) performing dry etching to the exposed ring of wafer edge to remove the needle-like defects generated on the wafer edge.

Abstract translation: 本发明涉及一种在蚀刻工艺中减少在晶片边缘上产生的针状缺陷的方法，其中使用光致抗蚀剂材料和硬掩模材料两者的蚀刻工艺作为掩模。 在去除光致抗蚀剂材料和硬掩模材料之后，所述方法包括以下步骤：（i）再次将光致抗蚀剂材料沉积在晶片上; （ii）进行晶片边缘曝光（WEE）以形成晶片边缘的环; 和（iii）对暴露的晶片边缘的环进行干蚀刻以去除在晶片边缘上产生的针状缺陷。

公开(公告)号：US20040009672A1

公开(公告)日：2004-01-15

申请号：US10192154

申请日：2002-07-11

Applicant: ProMos Technologies, Inc.

Inventor： Jefferson Lu ,  Nien-Yu Tsai

IPC: H01L021/311

CPC classification number: H01L21/76808 ,  H01L21/0276 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76232 ,  H01L21/76804

Abstract: A method for manufacturing a semiconductor device that includes providing a substrate, providing a dielectric layer over the substrate, depositing a layer of anti-reflective coating over the dielectric layer, providing a layer of photoresist over the layer of anti-reflective coating, patterning and defining the photoresist layer to provide a plurality of photoresist structures, wherein at least two adjacent photoresist structures provide a first distance, anisotropically etching the layer of anti-reflective coating unmasked by the photoresist structures to remove only a portion of the anti-reflective coating layer, etching the anti-reflective coating to completely remove the layer of anti-reflective coating unmasked by the photoresist structures, and etching the dielectric layer to form at least one trench between the at least two adjacent photoresist structures, wherein the first distance is substantially equal to a second distance defining an opening at the top of the trench.