公开(公告)号：US20100227471A1

公开(公告)日：2010-09-09

申请号：US12399372

申请日：2009-03-06

申请人： Pak K. Leung ,  Terry G. Sparks ,  David V. Horak ,  Steven M. Gates

发明人： Pak K. Leung ,  Terry G. Sparks ,  David V. Horak ,  Steven M. Gates

IPC分类号： H01L21/4763 ,  H01R43/00

CPC分类号： H01L21/76828 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76835 ,  H01L2221/1036 ,  Y10T29/49224

摘要： A method and apparatus are described for fabricating an ultra low-k interconnect structure by depositing and curing a first via layer (43) of ultra low dielectric constant (ULK) material, depositing a second uncured trench layer (51) of the same ULK material, selectively etching a via opening (62) and trench opening (72) with a dual damascene etch process which uses a trench etch end point signal from the chemical differences between uncured trench layer (51) and the underlying cured via layer (43), and then curing the second trench layer (83) before forming an interconnect structure (91) by filling the trench opening (72) and via opening (62) with an interconnection material so that there is no additional interface or higher dielectric constant material left behind.

摘要翻译： 描述了通过沉积和固化超低介电常数（ULK）材料的第一通孔层（43）来制造超低k互连结构的方法和装置，沉积相同ULK材料的第二未固化沟槽层（51） 通过使用来自未固化沟槽层（51）和下面的固化通孔层（43）之间的化学差异的沟槽蚀刻终点信号的双镶嵌蚀刻工艺来选择性地蚀刻通孔开口（62）和沟槽开口（72） 然后在通过用互连材料填充沟槽开口（72）和通孔开口（62）形成互连结构（91）之前固化第二沟槽层（83），使得不存在附加的界面或更高的介电常数材料留下 。