公开(公告)号：US20100227471A1

公开(公告)日：2010-09-09

申请号：US12399372

申请日：2009-03-06

申请人： Pak K. Leung ,  Terry G. Sparks ,  David V. Horak ,  Steven M. Gates

发明人： Pak K. Leung ,  Terry G. Sparks ,  David V. Horak ,  Steven M. Gates

IPC分类号： H01L21/4763 ,  H01R43/00

CPC分类号： H01L21/76828 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76835 ,  H01L2221/1036 ,  Y10T29/49224

摘要： A method and apparatus are described for fabricating an ultra low-k interconnect structure by depositing and curing a first via layer (43) of ultra low dielectric constant (ULK) material, depositing a second uncured trench layer (51) of the same ULK material, selectively etching a via opening (62) and trench opening (72) with a dual damascene etch process which uses a trench etch end point signal from the chemical differences between uncured trench layer (51) and the underlying cured via layer (43), and then curing the second trench layer (83) before forming an interconnect structure (91) by filling the trench opening (72) and via opening (62) with an interconnection material so that there is no additional interface or higher dielectric constant material left behind.

摘要翻译： 描述了通过沉积和固化超低介电常数（ULK）材料的第一通孔层（43）来制造超低k互连结构的方法和装置，沉积相同ULK材料的第二未固化沟槽层（51） 通过使用来自未固化沟槽层（51）和下面的固化通孔层（43）之间的化学差异的沟槽蚀刻终点信号的双镶嵌蚀刻工艺来选择性地蚀刻通孔开口（62）和沟槽开口（72） 然后在通过用互连材料填充沟槽开口（72）和通孔开口（62）形成互连结构（91）之前固化第二沟槽层（83），使得不存在附加的界面或更高的介电常数材料留下 。

公开(公告)号：US07247552B2

公开(公告)日：2007-07-24

申请号：US11033009

申请日：2005-01-11

申请人： Scott K. Pozder ,  Kevin J. Hess ,  Pak K. Leung ,  Edward O. Travis ,  Brett P. Wilkerson ,  David G. Wontor ,  Jie-Hua Zhao

发明人： Scott K. Pozder ,  Kevin J. Hess ,  Pak K. Leung ,  Edward O. Travis ,  Brett P. Wilkerson ,  David G. Wontor ,  Jie-Hua Zhao

IPC分类号： H01L21/4763

CPC分类号： H01L24/10 ,  H01L23/522 ,  H01L24/02 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00

摘要： A technique for alleviating the problems of defects caused by stress applied to bond pads (32) includes, prior to actually making an integrated circuit (10), adding dummy metal lines (74, 76) to interconnect layers (18, 22, 26) to increase the metal density of the interconnect layers. These problems are more likely when the interlayer dielectrics (16, 20, 24) between the interconnect layers are of a low-k material. A critical area or force area (64) around and under each bond pad defines an area in which a defect may occur due to a contact made to that bond pad. Any interconnect layer in such a critical area that has a metal density below a certain percentage can be the cause of a defect in the interconnect layers. Any interconnect layer that has a metal density below that percentage in the critical area has dummy metal lines added to it.

摘要翻译： 减轻施加到接合焊盘（32）的应力引起的缺陷的问题的技术包括：在实际制造集成电路（10）之前，将互连层（18,22,26）中的虚设金属线（74,76） 以增加互连层的金属密度。 当互连层之间的层间电介质（16,20,24）为低k材料时，这些问题更有可能。 在每个接合垫周围和之下的临界区域或力区域（64）限定了由于与该接合焊盘的接触而可能发生缺陷的区域。 金属密度低于某一百分比的这样关键区域中的任何互连层可能是互连层中缺陷的原因。 在临界区域中具有低于该百分比的金属密度的任何互连层都添加有虚拟金属线。

公开(公告)号：US5886867A

公开(公告)日：1999-03-23

申请号：US814627

申请日：1997-03-10

申请人： Vasanta Chivukula ,  Pak K. Leung

发明人： Vasanta Chivukula ,  Pak K. Leung

IPC分类号： H01L21/02 ,  H01L27/115 ,  H01G4/06 ,  H01L29/76

CPC分类号： H01L27/11502 ,  H01L28/55

摘要： A ferroelectric dielectric for microwave applications is provided including a polycrystalline perovskite phase of lead zirconate titanate dielectric material. Small grain size material is provided by a low temperature process, by a rapid thermal annealing process. A layer of amorphous ferroelectric precursor material is deposited and annealed in an oxygen containing atmosphere in the presence of water vapour, preferably with the addition of a few percent of ozone, and at a temperature of less than 500.degree. C. Advantageously, the method provides for formation of a ferroelectric material including lead zirconate titanate with a grain size less than 20 nm, with low film stress, high dielectric constant and low leakage current, which has excellent ferroelectric characteristics up to 10 GHz. This material has applications for capacitors, as filters, decoupling, coupling, and bypass elements and also for high frequency surface acoustic wave devices.

摘要翻译： 提供了用于微波应用的铁电电介质，其包括锆钛酸铅电介质材料的多晶钙钛矿相。 通过快速热退火工艺，通过低温工艺提供小晶粒尺寸的材料。 在水蒸气存在下，优选加入少量臭氧，并在低于500℃的温度下，在含氧气氛中沉积并退火一层非晶铁电前体材料。有利地，该方法提供 用于形成具有低于20nm的粒度小于20nm的锆钛酸铅的铁电体材料，具有低膜应力，高介电常数和低漏电流，其具有优异的高达10GHz的铁电特性。 该材料适用于电容器，滤波器，去耦，耦合和旁路元件以及高频表面声波器件。

公开(公告)号：US5753945A

公开(公告)日：1998-05-19

申请号：US595116

申请日：1996-02-01

申请人： Vasanta Chivukula ,  Pak K. Leung

发明人： Vasanta Chivukula ,  Pak K. Leung

IPC分类号： H01L21/02 ,  H01L29/51 ,  H01L29/76

CPC分类号： H01L28/56 ,  H01L28/60 ,  H01L29/516

摘要： An integrated circuit structure including dielectric barrier layer compatible with perovskite ferroelectric materials and comprising zirconium titanium oxide, ZrTiO.sub.4, and a method of formation of the dielectric barrier layer by sol gel process is described. The amorphous, mixed oxide barrier layer has excellent dielectric properties up to GHz frequencies, and crystallizes above 800.degree. C., facilitating device processing. In particular, the barrier layer is compatible with lead containing perovskites, including PZT and PLZT ferroelectric dielectrics for example for application in non-volatile memory cells, and high value capacitors for integrated circuits, using silicon or GaAs integrated circuit technologies.

摘要翻译： 描述了包括与钙钛矿铁电材料兼容并且包含锆钛氧化物，ZrTiO 4的电介质阻挡层的集成电路结构，以及通过溶胶凝胶法形成介电阻挡层的方法。 无定形混合氧化物阻挡层具有高达GHz频率的优良介电特性，并在800℃以上结晶，便于器件加工。 特别地，阻挡层与使用硅或GaAs集成电路技术的含铅钙钛矿相容，包括例如用于非易失性存储单元的PZT和PLZT铁电介质以及用于集成电路的高价值电容器。

公开(公告)号：US4778745A

公开(公告)日：1988-10-18

申请号：US29025

申请日：1987-03-23

申请人： Pak K. Leung

发明人： Pak K. Leung

IPC分类号： G01N21/956 ,  G03F1/00 ,  G03C5/00

CPC分类号： G03F1/84 ,  G01N21/95607

摘要： A method of detecting opaque defects on a reticle used to define die patterns during semiconductor device fabrication in which a comparison is made of reflected light levels between an image die containing the developed photo-sensitive resist of a top layer with a reference die which contains only previously formed layers. The comparison is limited to areas of the device where there is no image pattern formed by the resist. A defect is detected whenever there is a difference in the recorded levels detected during the comparison.

摘要翻译： 在半导体器件制造期间检测用于限定管芯图案的掩模版上的不透明缺陷的方法，其中比较包含顶层的显影光敏抗蚀剂的图像裸片与仅包含底层的参考裸片的反射光级别 以前形成的层。 该比较限于不存在由抗蚀剂形成的图像图案的装置的区域。 每当在比较期间检测到的记录水平存在差异时，检测到缺陷。

公开(公告)号：US5563762A

公开(公告)日：1996-10-08

申请号：US348849

申请日：1994-11-28

申请人： Pak K. Leung ,  Ismail T. Emesh

发明人： Pak K. Leung ,  Ismail T. Emesh

IPC分类号： H01L21/8247 ,  H01L21/02 ,  H01L21/768 ,  H01L21/77 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/00 ,  H01L27/04 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/788 ,  H01L29/792 ,  H01G4/30

CPC分类号： H01L28/55 ,  H01L21/76895 ,  H01L28/60 ,  Y10S148/014

摘要： A capacitor structure and method of forming a capacitor structure for an integrated circuit is provided. The capacitor structure, comprising a bottom electrode, capacitor dielectric and top electrode, is formed on a passivation layer overlying the interconnect metallization. The capacitor electrodes are interconnected to the underlying integrated circuit from underneath, through conductive vias, to the underlying interconnect metallization. The method provides for adding capacitors to an otherwise completed and passivated integrated circuit. The structure is particularly applicable for ferroelectric capacitors. The passivation layer acts as a barrier layer for a ferroelectric dielectric. Large area on-chip capacitors may added without affecting the interconnect routing or packing density of the underlying devices, and may be added almost independently of the process technology used formation of the underlying integrated circuit.

摘要翻译： 提供一种形成集成电路的电容器结构的电容器结构和方法。 包括底部电极，电容器电介质和顶部电极的电容器结构形成在覆盖互连金属化的钝化层上。 电容器电极从下面通过导电通孔连接到下面的集成电路到下面的互连金属化。 该方法提供了将电容器添加到另外完成和钝化的集成电路中。 该结构特别适用于铁电电容器。 钝化层用作铁电介质的阻挡层。 可以添加大面积的片上电容器，而不影响底层器件的互连布线或封装密度，并且可以几乎独立于使用底层集成电路的形成工艺加工。

公开(公告)号：US07955968B2

公开(公告)日：2011-06-07

申请号：US12399372

申请日：2009-03-06

申请人： Pak K. Leung ,  Terry G. Sparks ,  David V. Horak ,  Stephen M. Gates

发明人： Pak K. Leung ,  Terry G. Sparks ,  David V. Horak ,  Stephen M. Gates

IPC分类号： H01L21/4763

CPC分类号： H01L21/76828 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76835 ,  H01L2221/1036 ,  Y10T29/49224

摘要： A method and apparatus are described for fabricating an ultra low-k interconnect structure by depositing and curing a first via layer (43) of ultra low dielectric constant (ULK) material, depositing a second uncured trench layer (51) of the same ULK material, selectively etching a via opening (62) and trench opening (72) with a dual damascene etch process which uses a trench etch end point signal from the chemical differences between uncured trench layer (51) and the underlying cured via layer (43), and then curing the second trench layer (83) before forming an interconnect structure (91) by filling the trench opening (72) and via opening (62) with an interconnection material so that there is no additional interface or higher dielectric constant material left behind.

摘要翻译： 描述了通过沉积和固化超低介电常数（ULK）材料的第一通孔层（43）来制造超低k互连结构的方法和装置，沉积相同ULK材料的第二未固化沟槽层（51） 通过使用来自未固化沟槽层（51）和下面的固化通孔层（43）之间的化学差异的沟槽蚀刻终点信号的双镶嵌蚀刻工艺来选择性地蚀刻通孔开口（62）和沟槽开口（72） 然后在通过用互连材料填充沟槽开口（72）和通孔开口（62）形成互连结构（91）之前固化第二沟槽层（83），使得不存在附加的界面或更高的介电常数材料留下 。

公开(公告)号：US06146905A

公开(公告)日：2000-11-14

申请号：US334655

申请日：1999-06-17

申请人： Vasanta Chivukula ,  Pak K. Leung

发明人： Vasanta Chivukula ,  Pak K. Leung

IPC分类号： H01G7/06

CPC分类号： H01G7/06 ,  C04B35/491 ,  C04B2235/658 ,  C04B2235/6588 ,  C04B2235/663 ,  C04B2235/768

摘要： A ferroelectric dielectric for microwave applications is provided comprising a polycrystalline perovskite phase of lead zirconate titanate dielectric material. Small grain size material is provided by a low temperature process, by a rapid thermal annealing process. A layer of amorphous ferroelectric precursor material is deposited and annealed in an oxygen containing atmosphere in the presence of water vapor, preferably with the addition of a few percent of ozone, and at a temperature of less than 500.degree. C. Advantageously, the method provides for formation of a ferroelectric material comprising lead zirconate titanate with a grain size less than 20 nm, with low film stress, high dielectric constant and low leakage current, which has excellent ferroelectric characteristics up to 10 GHz. This material has applications for capacitors, as filters, decoupling, coupling, and bypass elements and also for high frequency surface acoustic wave devices.

摘要翻译： 提供了用于微波应用的铁电电介质，其包括钛酸铅锆酸盐电介质材料的多晶钙钛矿相。 通过快速热退火工艺，通过低温工艺提供小晶粒尺寸的材料。 在水蒸气存在下，优选加入少量臭氧，并在低于500℃的温度下，在含氧气氛中沉积并退火一层非晶铁电前体材料。有利地，该方法提供 用于形成具有低于20nm的粒径小于20nm的锆钛酸铅的铁电材料，具有低至10GHz的优异的铁电特性，具有低膜应力，高介电常数和低漏电流。 该材料适用于电容器，滤波器，去耦，耦合和旁路元件以及高频表面声波器件。

公开(公告)号：US06077715A

公开(公告)日：2000-06-20

申请号：US764367

申请日：1996-12-12

申请人： Vasanta Chivukula ,  Pak K. Leung

发明人： Vasanta Chivukula ,  Pak K. Leung

IPC分类号： H01L21/02 ,  H01L27/115

CPC分类号： H01L27/11502 ,  H01L28/55

摘要： A ferroelectric dielectric for microwave applications is provided comprising a polycrystalline perovskite phase of lead zirconate titanate dielectric material. Small grain size material is provided by a low temperature process, by a rapid thermal annealing process. A layer of amorphous ferroelectric precursor material is deposited and annealed in an oxygen containing atmosphere in the presence of water vapour, preferably with the addition of a few percent of ozone, and at a temperature of less than 500.degree. C. Advantageously, the method provides for formation of a ferroelectric material comprising lead zirconate titanate with a grain size less than 20 nm, with low film stress, high dielectric constant and low leakage current, which has excellent ferroelectric characteristics up to 10 GHz. This material has applications for capacitors, as filters, decoupling, coupling, and bypass elements and also for high frequency surface acoustic wave devices.

摘要翻译： 提供了用于微波应用的铁电电介质，其包括钛酸铅锆酸盐电介质材料的多晶钙钛矿相。 通过快速热退火工艺，通过低温工艺提供小晶粒尺寸的材料。 在水蒸气存在下，优选加入少量臭氧，并在低于500℃的温度下，在含氧气氛中沉积并退火一层非晶铁电前体材料。有利地，该方法提供 用于形成具有低于20nm的粒径小于20nm的锆钛酸铅的铁电材料，具有低至10GHz的优异的铁电特性，具有低膜应力，高介电常数和低漏电流。 该材料适用于电容器，滤波器，去耦，耦合和旁路元件以及高频表面声波器件。

公开(公告)号：US5789303A

公开(公告)日：1998-08-04

申请号：US680286

申请日：1996-07-11

申请人： Pak K. Leung ,  Ismail T. Emesh

发明人： Pak K. Leung ,  Ismail T. Emesh

IPC分类号： H01L21/8247 ,  H01L21/02 ,  H01L21/768 ,  H01L21/77 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/00 ,  H01L27/04 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/788 ,  H01L29/792 ,  H01L21/20

CPC分类号： H01L28/55 ,  H01L21/76895 ,  H01L28/60 ,  Y10S148/014

摘要： A capacitor structure and method of forming a capacitor structure for an integrated circuit is provided. The capacitor structure, comprising a bottom electrode, capacitor dielectric and top electrode, is formed on a passivation layer overlying the interconnect metallization. The capacitor electrodes are interconnected to the underlying integrated circuit from underneath, through conductive vias, to the underlying interconnect metallization. The method provides for adding capacitors to an otherwise completed and passivated integrated circuit. The structure is particularly applicable for ferroelectric capacitors. The passivation layer acts as a barrier layer for a ferroelectric dielectric. Large area on-chip capacitors may added without affecting the interconnect routing or packing density of the underlying devices, and may be added almost independently of the process technology used formation of the underlying integrated circuit.

摘要翻译： 提供一种形成集成电路的电容器结构的电容器结构和方法。 包括底部电极，电容器电介质和顶部电极的电容器结构形成在覆盖互连金属化的钝化层上。 电容器电极从下面通过导电通孔连接到下面的集成电路到下面的互连金属化。 该方法提供了将电容器添加到另外完成和钝化的集成电路中。 该结构特别适用于铁电电容器。 钝化层用作铁电介质的阻挡层。 可以添加大面积的片上电容器，而不影响底层器件的互连布线或封装密度，并且可以几乎独立于使用底层集成电路的形成工艺加工。