公开(公告)号：US12068392B2

公开(公告)日：2024-08-20

申请号：US17654807

申请日：2022-03-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chun Hsiung Tsai ,  Cheng-Yi Peng ,  Yin-Pin Wang ,  Kuo-Feng Yu ,  Da-Wen Lin ,  Jian-Hao Chen ,  Shahaji B. More

IPC分类号： H01L29/66 ,  H01L21/223 ,  H01L21/265 ,  H01L21/324 ,  H01L21/768 ,  H01L21/8234

CPC分类号： H01L29/665 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/324 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76825 ,  H01L21/76831 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/66515 ,  H01L29/66795

摘要： A method and structure for doping source and drain (S/D) regions of a PMOS and/or NMOS FinFET device are provided. In some embodiments, a method includes providing a substrate including a fin extending therefrom. In some examples, the fin includes a channel region, source/drain regions disposed adjacent to and on either side of the channel region, a gate structure disposed over the channel region, and a main spacer disposed on sidewalls of the gate structure. In some embodiments, contact openings are formed to provide access to the source/drain regions, where the forming the contact openings may etch a portion of the main spacer. After forming the contact openings, a spacer deposition and etch process may be performed. In some cases, after performing the spacer deposition and etch process, a silicide layer is formed over, and in contact with, the source/drain regions.

公开(公告)号：US12051620B2

公开(公告)日：2024-07-30

申请号：US17845891

申请日：2022-06-21

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Hung-Chang Sun ,  Po-Chin Chang ,  Akira Mineji ,  Zi-Wei Fang ,  Pinyen Lin

IPC分类号： H01L21/768 ,  H01L21/8234 ,  H01L23/532 ,  H01L23/535 ,  H01L27/088

CPC分类号： H01L21/76837 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76825 ,  H01L21/76829 ,  H01L21/76895 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/53295 ,  H01L23/535 ,  H01L27/088

摘要： A method for forming a semiconductor structure includes forming a gate structure on a substrate; depositing a first dielectric layer over the gate structure; depositing a second dielectric layer over the first dielectric layer and having a different density than the first dielectric layer; performing a first etching process on the first and second dielectric layers to form a trench; performing a second etching process on the first and second dielectric layers to modify the trench; filling a conductive material in the modified trench.

公开(公告)号：US20240145596A1

公开(公告)日：2024-05-02

申请号：US18402173

申请日：2024-01-02

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Su-Hao Liu ,  Kuo-Ju Chen ,  Kai-Hsuan Lee ,  I-Hsieh Wong ,  Cheng-Yu Yang ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo ,  Syun-Ming Jang ,  Meng-Han Chou

IPC分类号： H01L29/78 ,  H01L21/266 ,  H01L21/3115 ,  H01L21/764 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/417 ,  H01L29/49 ,  H01L29/66

CPC分类号： H01L29/7851 ,  H01L21/266 ,  H01L21/31155 ,  H01L21/764 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/76831 ,  H01L21/76897 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L29/0847 ,  H01L29/41725 ,  H01L29/41766 ,  H01L29/41791 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/28518

摘要： A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the first spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source/drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source/drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends across the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.

公开(公告)号：US11955430B2

公开(公告)日：2024-04-09

申请号：US17219188

申请日：2021-03-31

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Chih-Hsuan Lin ,  Hsi Chung Chen ,  Ji-Ling Wu ,  Chih-Teng Liao

IPC分类号： H01L23/535 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L23/535 ,  H01L21/32136 ,  H01L21/76805 ,  H01L21/76819 ,  H01L21/76825 ,  H01L21/76895 ,  H01L23/5283 ,  H01L23/53257

摘要： A method of manufacturing a semiconductor device includes forming a first dielectric layer over a substrate, forming a metal layer in the first dielectric layer, forming an etch stop layer on a surface of the first dielectric layer and the metal layer, removing portions of the metal layer and the etch stop layer to form a recess in the metal layer, and forming a tungsten plug in the recess. The recess is spaced apart from a bottom surface of the etch stop layer.

公开(公告)号：US11948898B2

公开(公告)日：2024-04-02

申请号：US16413943

申请日：2019-05-16

申请人： Intel Corporation

发明人： Kristof Darmawikarta ,  Srinivas V. Pietambaram ,  Hongxia Feng ,  Xiaoying Guo ,  Benjamin T. Duong

IPC分类号： H01L23/66 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L23/66 ,  H01L21/76825 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76879 ,  H01L23/5283 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2223/6605

摘要： Conductive structures in a microelectronic package and having a surface roughness of 50 nm or less are described. This surface roughness is from 2 to 4 times less than can be found in packages with conductive structures (e.g., traces) formed using alternative techniques. This reduced surface roughness has a number of benefits, which in some cases includes a reduction of insertion loss and improves a signal to noise ratio for high frequency computing applications. The reduced surface roughness can be accomplished by protecting the conductive structure r during etch processes and applying an adhesion promoting layer to the conductive structure.

公开(公告)号：US20230411150A1

公开(公告)日：2023-12-21

申请号：US18362136

申请日：2023-07-31

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Je-Ming Kuo ,  Yen-Chun Huang ,  Chih-Tang Peng ,  Tien-I Bao

IPC分类号： H01L21/02 ,  H01L29/06 ,  B05D7/00 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/762 ,  B05D3/06 ,  B05D1/38 ,  H01L21/768 ,  B05D1/00 ,  G03F7/16

CPC分类号： H01L21/02282 ,  H01L21/76828 ,  B05D7/546 ,  H01L21/823481 ,  H01L21/31111 ,  H01L21/02126 ,  H01L21/76224 ,  H01L21/0223 ,  H01L21/02164 ,  H01L21/02348 ,  H01L21/02323 ,  B05D3/067 ,  B05D1/38 ,  H01L21/76825 ,  B05D1/005 ,  H01L21/02255 ,  H01L21/76832 ,  H01L21/76826 ,  G03F7/162 ,  H01L29/0649

摘要： The present disclosure is generally related to semiconductor devices, and more particularly to a dielectric material formed in semiconductor devices. The present disclosure provides methods for forming a dielectric material layer by a cyclic spin-on coating process. In an embodiment, a method of forming a dielectric material on a substrate includes spin-coating a first portion of a dielectric material on a substrate, curing the first portion of the dielectric material on the substrate, spin-coating a second portion of the dielectric material on the substrate, and thermal annealing the dielectric material to form an annealed dielectric material on the substrate.

公开(公告)号：US20230395388A1

公开(公告)日：2023-12-07

申请号：US17829699

申请日：2022-06-01

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Li-Han LIN ,  Jr-Chiuan WANG ,  Szu-Yu HOU

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L27/108

CPC分类号： H01L21/31111 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76816 ,  H01L21/31144 ,  H01L27/10885 ,  H01L27/10888 ,  H01L21/76825

摘要： A method for manufacturing a semiconductor structure is provided. First, a first insulating layer is formed over a substrate, and a second insulating layer having an opening is formed over the first insulating layer. A conductive line structure is formed in the opening of the second insulating layer, thereby forming a contact void between the second insulating layer and the conductive line structure. A plasma oxide layer is conformally formed over the conductive line structure, the first insulating layer, and the contact void. A nitride capping layer is formed over the plasma oxide layer to fill the contact void. Then, nitrogen ions are introduced into a surface of the nitride capping layer surrounding the conductive line structure. An etching back process is performed to remove a portion of the nitride capping layer, thereby forming a refilled contact void between the first insulating layer and the conductive line structure.

公开(公告)号：US11804432B2

公开(公告)日：2023-10-31

申请号：US17173863

申请日：2021-02-11

申请人： Infineon Technologies AG

发明人： Markus Zundel ,  Sergey Ananiev ,  Andreas Behrendt ,  Holger Doepke ,  Uwe Schmalzbauer ,  Michael Sorger ,  Dominic Thurmer

IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L23/528 ,  H01L21/76825 ,  H01L21/76837 ,  H01L23/5329 ,  H01L2924/00 ,  H01L2924/0002

摘要： A semiconductor device includes a semiconductor substrate having a first main surface and a metal structure above the first main surface. The metal structure has a periphery region that includes a transition section along which the metal structure transitions from a first thickness to a second thickness less than the first thickness. A polymer-based insulating material contacts and covers at least the periphery region of the metal structure. A thickness of the polymer-based insulating material begins to increase on a first main surface of the metal structure that faces away from the semiconductor substrate and continues to increase in a direction towards the transition section. An average slope of a surface of the polymer-based insulating material which faces away from the semiconductor substrate, as measured with respect to the first main surface of the metal structure, is less than 60 degrees along the periphery region of the metal structure.

公开(公告)号：US11710659B2

公开(公告)日：2023-07-25

申请号：US17646024

申请日：2021-12-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Li-Chieh Wu ,  Tang-Kuei Chang ,  Kuo-Hsiu Wei ,  Kei-Wei Chen ,  Ying-Lang Wang ,  Su-Hao Liu ,  Kuo-Ju Chen ,  Liang-Yin Chen ,  Huicheng Chang ,  Ting-Kui Chang ,  Chia Hsuan Lee

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L29/66 ,  H01L29/78 ,  H01L23/485 ,  H01L21/3115 ,  H01L23/532

CPC分类号： H01L21/76883 ,  H01L21/76825 ,  H01L23/5226 ,  H01L21/31155 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76886 ,  H01L23/485 ,  H01L23/5329 ,  H01L23/53295 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

摘要： The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.

公开(公告)号：US11705365B2

公开(公告)日：2023-07-18

申请号：US17323381

申请日：2021-05-18

申请人： Applied Materials, Inc.

发明人： Wei-Sheng Lei ,  Kurtis Leschkies ,  Roman Gouk ,  Giback Park ,  Kyuil Cho ,  Tapash Chakraborty ,  Han-Wen Chen ,  Steven Verhaverbeke

IPC分类号： H01L21/768 ,  H01L21/48

CPC分类号： H01L21/76825 ,  H01L21/486 ,  H01L21/76877

摘要： The present disclosure relates to micro-via structures for interconnects in advanced wafer level semiconductor packaging. The methods described herein enable the formation of high-quality, low-aspect-ratio micro-via structures with improved uniformity, thus facilitating thin and small-form-factor semiconductor devices having high I/O density with improved bandwidth and power.