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公开(公告)号：US10340868B2
公开(公告)日：2019-07-02
申请号：US15594075
申请日：2017-05-12
Inventor： Koji Obata , Kazuo Matsukawa
Abstract: An amplifier circuit includes a first input branch circuit including a first sampling capacitor, a second input branch circuit including a second sampling capacitor, an averaging capacitor, and a subtraction capacitor, a feedback capacitor, and an operational amplifier. The first sampling capacitor samples an input voltage in a first time period and outputs a first voltage. The second sampling capacitor samples the input voltage in the first time period and outputs a second voltage. The averaging capacitor takes an average of the second voltage in the second time period and outputs a third voltage. The subtraction capacitor receives the third voltage in the first time period. The subtraction capacitor subtracts the first voltage from the third voltage and outputs a fourth voltage in the second time period. The operational amplifier is connected to the feedback capacitor and amplifies the fourth voltage. The first and second time periods are repeated alternately.
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公开(公告)号：US09654135B2
公开(公告)日：2017-05-16
申请号：US15160010
申请日：2016-05-20
Inventor： Takuji Miki , Kazuo Matsukawa
CPC classification number: H03M1/468 , H03M1/0626 , H03M1/0665
Abstract: An AD converter converts an analogue input voltage into a digital value including a most significant bit to a least significant bit. The AD converter includes: a common node; a capacitive DAC; a comparator; a successive approximation controller; and an integrator. The integrator includes first to Xth integrating circuits connected in a cascade arrangement, where X is an integer greater than or equal to two, and at least one feedforward path that each samples a residual voltage and outputs the sampled residual voltage to one of the second to Xth integrating circuits.
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