公开(公告)号：US20170320457A1

公开(公告)日：2017-11-09

申请号：US15522138

申请日：2015-11-27

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： KATSUMI KAKIMOTO ,  HIROSHI YAMANAKA ,  TAKANORI SUGIYAMA ,  ISAO HATTORI ,  YUICHI HIGUCHI ,  HIDEYUKI ARAI ,  YOSUKE HAGIHARA

IPC: B60R21/015 ,  G01J1/02 ,  B60H1/00 ,  B60R16/02 ,  H01L35/32 ,  G01V8/12

CPC classification number: B60R21/01532 ,  B60H1/00 ,  B60H1/00878 ,  B60R16/02 ,  G01J1/02 ,  G01V8/12 ,  H01L35/32

Abstract: A detection device is used with a vehicle including a cabin, a ceiling, pillars, a driver seat, and a passenger seat. The detection device includes a detector disposed on the ceiling or the pillars of the vehicle and detecting an object in the cabin while not contacting the object, and a scanning unit that moves the detector for scan. The detection device can detect a temperature of the object accurately, and control air-conditioning comfortably to the object.

公开(公告)号：US20160181228A1

公开(公告)日：2016-06-23

申请号：US15053868

申请日：2016-02-25

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： YUICHI HIGUCHI ,  HIDEYUKI ARAI

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48

Abstract: A semiconductor device includes a first laminated body and a second laminated body. The first laminated body includes sequentially a first element, a first wiring layer, and a first connection layer that includes a first junction electrode, on a main surface of a first substrate. The second laminated body includes sequentially a second element, a second wiring layer, and a second connection layer that includes a second junction electrode, on a main surface of a semiconductor substrate. The first laminated body and the second laminated body are bonded by directly bonding the first junction electrode and the second junction electrode with the two junction electrodes facing each other. A space region is formed at a part of a junction interface between the first laminated body and the second laminated body.

Abstract translation: 半导体器件包括第一层叠体和第二层叠体。 第一层叠体在第一基板的主表面上依次包括第一元件，第一布线层和包括第一接合电极的第一连接层。 第二层叠体在半导体衬底的主表面上依次包括第二元件，第二布线层和包括第二接合电极的第二连接层。 第一层叠体和第二层叠体通过将两个接合电极面对的第一接合电极和第二接合电极直接接合而接合。 在第一层叠体和第二层叠体之间的接合界面的一部分处形成有空间区域。