公开(公告)号：US20150172723A1

公开(公告)日：2015-06-18

申请号：US14629747

申请日：2015-02-24

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hiroshi AMANO ,  Takeshi TANAKA ,  Takashi HASHIMOTO ,  Yoshiteru HAYASHI

IPC: H04N19/82 ,  H04N19/513

CPC classification number: H04N19/82 ,  H04N19/117 ,  H04N19/43 ,  H04N19/44 ,  H04N19/513 ,  H04N19/61

Abstract: A moving image decoding apparatus which enables reduction in the memory bandwidth and the memory access latency for the motion compensation filter coefficients for use in inter-picture prediction involving motion compensation using variable coefficients includes: a decoding unit (101) which decodes, from a coded stream, a plurality of motion compensation filter coefficients; a memory (109) for holding the motion compensation filter coefficients included in the coded stream; a filter coefficient storage unit (103) for holding at least one of the motion compensation filter coefficients which is required for the motion compensation; a motion compensation unit (107) which performs motion compensation using the required motion compensation filter coefficient held in the filter coefficient storage unit; and a filter coefficient transfer control unit (102) which writes, in the memory, the motion compensation filter coefficients decoded by the decoding unit, and transfers the required motion compensation filter coefficient from the memory to the filter coefficient storage unit, only when the required coefficient is not yet stored therein.

Abstract translation: 一种运动图像解码装置，其能够减少使用可变系数的运动补偿的帧间预测中使用的运动补偿滤波器系数的存储器带宽和存储器访问等待时间，包括：解码单元， 流，多个运动补偿滤波器系数; 用于保持包含在编码流中的运动补偿滤波器系数的存储器（109） 滤波器系数存储单元，用于保持运动补偿所需的运动补偿滤波器系数中的至少一个; 使用保持在滤波器系数存储单元中的所需运动补偿滤波器系数进行运动补偿的运动补偿单元（107） 以及滤波器系数传递控制单元（102），其在存储器中写入由解码单元解码的运动补偿滤波器系数，并且将所需的运动补偿滤波器系数从存储器传送到滤波器系数存储单元，只有当所需的 系数尚未存储在其中。

公开(公告)号：US20220197972A1

公开(公告)日：2022-06-23

申请号：US17691590

申请日：2022-03-10

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Yoshiteru HAYASHI

IPC: G06F17/15

Abstract: An arithmetic processing system includes an external memory and an arithmetic-logic unit. The arithmetic-logic unit performs at least operations of 1) acquiring a first partition map from each input feature map stored in the external memory, the first partition map being one of partition maps included in the input feature map; executing a convolution operation on the first partition maps acquired from the external memory; storing, in the external memory, first partition maps that have undergone the convolution operation, and 2) acquiring a second partition map from each input feature map stored in the external memory, the second partition map being one of the partition maps; executing a convolution operation on the second partition maps acquired from the external memory; and storing, in the external memory, second partition maps that have undergone the convolution operation.

公开(公告)号：US20230305719A1

公开(公告)日：2023-09-28

申请号：US18122950

申请日：2023-03-17

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hiroki MONTA ,  Yoshiteru HAYASHI

IPC: G06F3/06

CPC classification number: G06F3/0626 ,  G06F3/0659 ,  G06F3/0683

Abstract: A data storage system is a data storage system which is mounted on a moving body. The data storage system includes: a plurality of ECUs which are connected to a network in the moving body; a shared storage device into which data is writable by each of the plurality of ECUs; and a shared priority controller which is connected between the plurality of ECUs and the shared storage device, and controls an order of priority in which data is written into the shared storage device from each of the plurality of ECUs.

公开(公告)号：US20210342160A1

公开(公告)日：2021-11-04

申请号：US17375574

申请日：2021-07-14

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Yoshiteru HAYASHI

IPC: G06F9/38 ,  G06F9/30

Abstract: A processor performs, in accordance with a single instruction, multiplication processing and comparison processing. The multiplication processing includes obtaining a multiplication result by multiplying together a first data element and a first value. The comparison processing includes comparing the multiplication result with a second data element. The first data element is stored in a first register, the second data element is stored in a second register, and the first value is stored in a third register.