公开(公告)号：US07389360B1

公开(公告)日：2008-06-17

申请号：US09985676

申请日：2001-11-05

Applicant: Pankaj Patel ,  Viswesh Ananthakrishnan

Inventor： Pankaj Patel ,  Viswesh Ananthakrishnan

IPC: G06F15/173

CPC classification number: H04L45/00 ,  H04L45/56 ,  H04L45/60 ,  H04L45/742

Abstract: A key engine that performs route lookups for a plurality of keys may include a data processing portion configured to process one data item at a time and to request data when needed. A buffer may be configured to store a partial result from the data processing portion. A controller may be configured to load the partial result from the data processing portion into the buffer. The controller also may be configured to input another data item into the data processing portion for processing while requested data is obtained for a prior data item. A number of these key engines may be used by a routing unit to perform a large number of route lookups at the same time.

Abstract translation: 执行多个键的路线查找的关键引擎可以包括被配置为一次处理一个数据项并在需要时请求数据的数据处理部分。 可以将缓冲器配置为存储来自数据处理部分的部分结果。 控制器可以被配置为将来自数据处理部分的部分结果加载到缓冲器中。 控制器还可以被配置为在对于先前的数据项获得所请求的数据的同时，将另一数据项输入数据处理部分进行处理。 路由单元可以使用许多这些密钥引擎来同时执行大量的路由查找。

公开(公告)号：US08611216B2

公开(公告)日：2013-12-17

申请号：US13250765

申请日：2011-09-30

Applicant: Dennis C. Ferguson ,  Philippe Lacroute ,  Chi-Chung Chen ,  Gerald Cheung ,  Tatao Chuang ,  Pankaj Patel ,  Viswesh Ananthakrishnan

Inventor： Dennis C. Ferguson ,  Philippe Lacroute ,  Chi-Chung Chen ,  Gerald Cheung ,  Tatao Chuang ,  Pankaj Patel ,  Viswesh Ananthakrishnan

IPC: H04J1/16 ,  H04L12/66 ,  H04L12/28

CPC classification number: H04L49/90 ,  H04L47/50 ,  H04L47/6225 ,  H04L49/3036 ,  H04L49/351 ,  H04L49/901 ,  H04L49/9094

Abstract: Ordering logic ensures that data items being processed by a number of parallel processing units are unloaded from the processing units in the original per-flow order that the data items were loaded into the parallel processing units. The ordering logic includes a pointer memory, a tail vector, and a head vector. Through these three elements, the ordering logic keeps track of a number of “virtual queues” corresponding to the data flows. A round robin arbiter unloads data items from the processing units only when a data item is at the head of its virtual queue.

Abstract translation: 订购逻辑确保由多个并行处理单元处理的数据项以原始每流顺序从处理单元卸载，数据项被加载到并行处理单元中。 排序逻辑包括指针存储器，尾部矢量和头部矢量。 通过这三个元素，排序逻辑跟踪与数据流相对应的多个“虚拟队列”。 循环仲裁器只有在数据项位于其虚拟队列的头部时才从处理单元中卸载数据项。

公开(公告)号：US07856510B1

公开(公告)日：2010-12-21

申请号：US12120729

申请日：2008-05-15

Applicant: Pankaj Patel ,  Viswesh Ananthakrishnan

Inventor： Pankaj Patel ,  Viswesh Ananthakrishnan

IPC: G06F15/173

CPC classification number: H04L45/00 ,  H04L45/56 ,  H04L45/60 ,  H04L45/742

Abstract: A key engine that performs route lookups for a plurality of keys may include a data processing portion configured to process one data item at a time and to request data when needed. A buffer may be configured to store a partial result from the data processing portion. A controller may be configured to load the partial result from the data processing portion into the buffer. The controller also may be configured to input another data item into the data processing portion for processing while requested data is obtained for a prior data item. A number of these key engines may be used by a routing unit to perform a large number of route lookups at the same time.

Abstract translation: 执行多个键的路线查找的关键引擎可以包括被配置为一次处理一个数据项并在需要时请求数据的数据处理部分。 可以将缓冲器配置为存储来自数据处理部分的部分结果。 控制器可以被配置为将来自数据处理部分的部分结果加载到缓冲器中。 控制器还可以被配置为在对于先前的数据项获得请求的数据的同时，将另一数据项输入数据处理部分进行处理。 路由单元可以使用许多这些密钥引擎来同时执行大量的路由查找。

公开(公告)号：US07764606B1

公开(公告)日：2010-07-27

申请号：US11755292

申请日：2007-05-30

Applicant: Dennis C. Ferguson ,  Philippe Lacroute ,  Chi-Chung Chen ,  Gerald Cheung ,  Tatao Chuang ,  Pankaj Patel ,  Viswesh Ananthakrishnan

Inventor： Dennis C. Ferguson ,  Philippe Lacroute ,  Chi-Chung Chen ,  Gerald Cheung ,  Tatao Chuang ,  Pankaj Patel ,  Viswesh Ananthakrishnan

IPC: H04L1/00 ,  H04L12/56 ,  H04L12/28

CPC classification number: H04L49/90 ,  H04L47/50 ,  H04L47/6225 ,  H04L49/3036 ,  H04L49/351 ,  H04L49/901 ,  H04L49/9094

Abstract: Ordering logic ensures that data items being processed by a number of parallel processing units are unloaded from the processing units in the original per-flow order that the data items were loaded into the parallel processing units. The ordering logic includes a pointer memory, a tail vector, and a head vector. Through these three elements, the ordering logic keeps track of a number of “virtual queues” corresponding to the data flows. A round robin arbiter unloads data items from the processing units only when a data item is at the head of its virtual queue.

Abstract translation: 订购逻辑确保由多个并行处理单元处理的数据项以原始每流顺序从处理单元卸载，数据项被加载到并行处理单元中。 排序逻辑包括指针存储器，尾部矢量和头部矢量。 通过这三个元素，排序逻辑跟踪与数据流相对应的多个“虚拟队列”。 循环仲裁器只有在数据项位于其虚拟队列的头部时才从处理单元中卸载数据项。