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1.发明授权Method and apparatus for staggering execution of a single packed data instruction using the same circuit 有权用于使用相同电路交错执行单个打包数据指令的方法和装置公开(公告)号：US06687810B2
公开(公告)日：2004-02-03
申请号：US10164976
申请日：2002-06-06
IPC分类号： G06F1500
CPC分类号： G06F9/30014 , G06F9/30036 , G06F9/3826 , G06F9/3828 , G06F9/3875 , G06F9/3885
摘要： A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.
摘要翻译： 公开了一种用于交错执行指令的方法和装置。 根据本发明的一个实施例，接收单个宏指令，其中单个宏指令指定至少两个逻辑寄存器，并且其中两个逻辑寄存器分别存储具有相应数据元素的第一和第二压缩数据操作数。 然后，使用相同的电路，在来自所述第一和第二打包数据操作数的第一和第二多个相应数据元素上独立地执行由单个宏指令指定的操作，以独立地生成第一和第二多个结果数据元素 。 第一和第二多个结果数据元素作为第三打包数据操作数存储在单个逻辑寄存器中。
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公开(公告)号：US06694426B2
公开(公告)日：2004-02-17
申请号：US10164774
申请日：2002-06-06
IPC分类号： G06F1500
CPC分类号： G06F9/30014 , G06F9/30036 , G06F9/3826 , G06F9/3828 , G06F9/3875 , G06F9/3885
摘要： A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.
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公开(公告)号：US06425073B1
公开(公告)日：2002-07-23
申请号：US09805280
申请日：2001-03-13
IPC分类号： G06F900
摘要： A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.
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公开(公告)号：US07366881B2
公开(公告)日：2008-04-29
申请号：US11103702
申请日：2005-04-11
IPC分类号： G06F9/30
CPC分类号： G06F9/30014 , G06F9/30036 , G06F9/3826 , G06F9/3828 , G06F9/3875 , G06F9/3885
摘要： A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.
摘要翻译： 公开了一种用于交错执行指令的方法和装置。 根据本发明的一个实施例，接收单个宏指令，其中单个宏指令指定至少两个逻辑寄存器，并且其中两个逻辑寄存器分别存储具有相应数据元素的第一和第二压缩数据操作数。 然后，使用相同电路，在来自所述第一和第二打包数据操作数的第一和第二多个相应数据元素上独立地执行由单个宏指令指定的操作，以独立地生成第一和第二多个结果数据元素 。 第一和第二多个结果数据元素作为第三打包数据操作数存储在单个逻辑寄存器中。
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5.发明授权Staggering execution of a single packed data instruction using the same circuit 失效使用相同电路的单个打包数据指令的交错执行公开(公告)号：US06925553B2
公开(公告)日：2005-08-02
申请号：US10689291
申请日：2003-10-20
CPC分类号： G06F9/30014 , G06F9/30036 , G06F9/3826 , G06F9/3828 , G06F9/3875 , G06F9/3885
摘要： A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a macro instruction specifying an operation, and specifying a first and a second data operand in first and second registers, respectively, is received. The macro instruction is then split into a first micro instruction and a second micro instruction, the first micro instruction specifying the operation on a first corresponding segment including a first portion of the first data operand and a first portion of the second data operand, and the second micro instruction specifying the operation on a second corresponding segment including a second portion of the first data operand and a second portion of the second data operand. The first and second micro instructions are then executed.
摘要翻译： 公开了一种用于交错执行指令的方法和装置。 根据本发明的一个实施例，接收指定操作并分别在第一和第二寄存器中指定第一和第二数据操作数的宏指令。 然后，宏指令被分割成第一微指令和第二微指令，第一微指令指定在包括第一数据操作数的第一部分和第二数据操作数的第一部分的第一对应段上的操作，以及 指定在包括第一数据操作数的第二部分和第二数据操作数的第二部分的第二对应段上的操作的第二微指令。 然后执行第一和第二微指令。
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6.发明授权Method and apparatus for staggering execution of a single packed data instruction using the same circuit 失效用于使用相同电路交错执行单个打包数据指令的方法和装置公开(公告)号：US06230257B1
公开(公告)日：2001-05-08
申请号：US09053004
申请日：1998-03-31
IPC分类号： G06F738
CPC分类号： G06F9/30014 , G06F9/30036 , G06F9/3826 , G06F9/3828 , G06F9/3875 , G06F9/3885
摘要： A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.
摘要翻译： 公开了一种用于交错执行指令的方法和装置。 根据本发明的一个实施例，接收单个宏指令，其中单个宏指令指定至少两个逻辑寄存器，并且其中两个逻辑寄存器分别存储具有相应数据元素的第一和第二压缩数据操作数。 然后，使用相同电路，在来自所述第一和第二打包数据操作数的第一和第二多个相应数据元素上独立地执行由单个宏指令指定的操作，以独立地生成第一和第二多个结果数据元素 。 第一和第二多个结果数据元素作为第三打包数据操作数存储在单个逻辑寄存器中。
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公开(公告)号：US08347066B2
公开(公告)日：2013-01-01
申请号：US11069004
申请日：2005-02-28
IPC分类号： G06F9/38
CPC分类号： G06F9/3861
摘要： Replay instruction morphing. One disclosed apparatus includes an execution unit to execute an instruction. A replay system replays an altered instruction if the execution unit executes the instruction erroneously.
摘要翻译： 重播指示变形。 所公开的装置包括执行指令的执行单元。 如果执行单元错误地执行指令，则重放系统重放改变的指令。
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公开(公告)号：US06880069B1
公开(公告)日：2005-04-12
申请号：US09608567
申请日：2000-06-30
IPC分类号： G06F9/38
CPC分类号： G06F9/3861
摘要： Replay instruction morphing. One disclosed apparatus includes an execution unit to execute an instruction. A replay system replays an altered instruction if the execution unit executes the instruction erroneously.
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