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12 条记录 (耗时 0.019 秒)

    Method and apparatus for staggering execution of an instruction
    3.
    发明授权
    Method and apparatus for staggering execution of an instruction 有权

    公开(公告)号：US06425073B1

    公开(公告)日：2002-07-23

    申请号：US09805280

    申请日：2001-03-13

    申请人： Patrice Roussel ,  Glenn J. Hinton ,  Shreekant S. Thakkar ,  Brent R. Boswell ,  Karol F. Menezes

    发明人： Patrice Roussel ,  Glenn J. Hinton ,  Shreekant S. Thakkar ,  Brent R. Boswell ,  Karol F. Menezes

    IPC分类号： G06F900

    摘要： A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.

    Method and apparatus for staggering execution of a single packed data instruction using the same circuit
    5.
    发明授权
    Method and apparatus for staggering execution of a single packed data instruction using the same circuit 有权
    用于使用相同电路交错执行单个打包数据指令的方法和装置

    公开(公告)号：US06687810B2

    公开(公告)日：2004-02-03

    申请号：US10164976

    申请日：2002-06-06

    申请人： Patrice Roussel ,  Glenn J. Hinton ,  Shreekant S. Thakkar ,  Brent R. Boswell ,  Karol F. Menezes

    发明人： Patrice Roussel ,  Glenn J. Hinton ,  Shreekant S. Thakkar ,  Brent R. Boswell ,  Karol F. Menezes

    IPC分类号： G06F1500

    CPC分类号： G06F9/30014 ,  G06F9/30036 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/3875 ,  G06F9/3885

    摘要： A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.

    摘要翻译： 公开了一种用于交错执行指令的方法和装置。 根据本发明的一个实施例，接收单个宏指令，其中单个宏指令指定至少两个逻辑寄存器，并且其中两个逻辑寄存器分别存储具有相应数据元素的第一和第二压缩数据操作数。 然后，使用相同的电路，在来自所述第一和第二打包数据操作数的第一和第二多个相应数据元素上独立地执行由单个宏指令指定的操作，以独立地生成第一和第二多个结果数据元素 。 第一和第二多个结果数据元素作为第三打包数据操作数存储在单个逻辑寄存器中。

    Method and apparatus for generating an advanced encryption standard (AES) key schedule
    6.
    发明授权
    Method and apparatus for generating an advanced encryption standard (AES) key schedule 有权
    用于生成高级加密标准（AES）密钥调度的方法和装置

    公开(公告)号：US08787565B2

    公开(公告)日：2014-07-22

    申请号：US11841556

    申请日：2007-08-20

    申请人： Shay Gueron ,  Martin G. Dixon ,  Srinivas Chennupaty ,  Mayank Bomb ,  Brent R. Boswell

    发明人： Shay Gueron ,  Martin G. Dixon ,  Srinivas Chennupaty ,  Mayank Bomb ,  Brent R. Boswell

    IPC分类号： H04K1/00 ,  H04L9/00

    CPC分类号： H04L9/28 ,  G06F9/30007 ,  H04L9/0631 ,  H04L2209/125 ,  H04L2209/24

    摘要： An Advanced Encryption Standard (AES) key generation assist instruction is provided. The AES key generation assist instruction assists in generating round keys used to perform AES encryption and decryption operations. The AES key generation instruction operates independent of the size of the cipher key and performs key generation operations in parallel on four 32-bit words thereby increasing the speed at which the round keys are generated. This instruction is easy to use in software. Hardware implementation of this instruction removes potential threats of software (cache access based) side channel attacks on this part of the AES algorithm.

    摘要翻译： 提供了高级加密标准（AES）密钥生成辅助指令。 AES密钥生成辅助指令有助于生成用于执行AES加密和解密操作的循环密钥。 AES密钥生成指令独立于密码密钥的大小，并行执行四个32位字的密钥生成操作，从而增加生成循环密钥的速度。 该指令在软件中易于使用。 该指令的硬件实现可以消除这部分AES算法对软件（基于缓存访问的）侧面信道攻击的潜在威胁。

    METHOD, APPARATUS AND SYSTEM FOR CONFIGURING A PROTOCOL STACK OF AN INTEGRATED CIRCUIT CHIP
    9.
    发明申请
    METHOD, APPARATUS AND SYSTEM FOR CONFIGURING A PROTOCOL STACK OF AN INTEGRATED CIRCUIT CHIP 有权
    用于配置集成电路芯片的协议栈的方法，装置和系统

    公开(公告)号：US20150269108A1

    公开(公告)日：2015-09-24

    申请号：US14658021

    申请日：2015-03-13

    申请人： Bryan L. Spry ,  Marcus W. Song ,  Deepak M. Rangaraj ,  Avinash N. Ananthakrishnan ,  Robert J. Hayes ,  Aimee D. Wood ,  Adam E. Letendre ,  Brent R. Boswell

    发明人： Bryan L. Spry ,  Marcus W. Song ,  Deepak M. Rangaraj ,  Avinash N. Ananthakrishnan ,  Robert J. Hayes ,  Aimee D. Wood ,  Adam E. Letendre ,  Brent R. Boswell

    IPC分类号： G06F13/42

    CPC分类号： G06F13/4221 ,  G06F13/122 ,  G06F13/4265 ,  Y02D10/14 ,  Y02D10/151

    摘要： Techniques and mechanisms for configuring an integrated circuit (IC) chip to implement a protocol stack. In an embodiment, a transaction layer of the IC chip is operable to exchange with a link layer of the IC chip transaction layer packets (TLPs) having a format compatible with one defined in a Peripheral Component Interconnect Express™ (PCIe™) specification. Configuration circuitry of the IC chip provides for configuration of a first protocol stack including the transaction layer, circuitry of the link layer and a first physical layer of the IC chip. The configuration circuitry further provides for an alternative configuration of a second protocol stack including the transaction layer, circuitry of the link layer and a second physical layer of the IC chip. In another embodiment, the first protocol stack supports single-ended signaling to communicate TLP information, whereas the second protocol stack supports differential signaling to communicate TLP information.

    摘要翻译： 用于配置集成电路（IC）芯片以实现协议栈的技术和机制。 在一个实施例中，IC芯片的事务层可操作以与具有与外围组件互连Express（TM TM）规范中定义的格式兼容的格式的IC芯片事务层分组（TLP）的链路层进行交换。 IC芯片的配置电路提供包括交易层，链路层的电路和IC芯片的第一物理层的第一协议栈的配置。 配置电路还提供包括交易层，链路层的电路和IC芯片的第二物理层的第二协议栈的备选配置。 在另一实施例中，第一协议栈支持单端信令来传送TLP信息，而第二协议栈支持差分信令来传送TLP信息。

    Method and apparatus for staggering execution of an instruction
    10.
    发明授权
    Method and apparatus for staggering execution of an instruction 有权
    用于交错执行指令的方法和装置

    公开(公告)号：US07366881B2

    公开(公告)日：2008-04-29

    申请号：US11103702

    申请日：2005-04-11

    申请人： Patrice Roussel ,  Glenn J. Hinton ,  Shreekant S. Thakkar ,  Brent R. Boswell ,  Karol F. Menezes

    发明人： Patrice Roussel ,  Glenn J. Hinton ,  Shreekant S. Thakkar ,  Brent R. Boswell ,  Karol F. Menezes

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30014 ,  G06F9/30036 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/3875 ,  G06F9/3885

    摘要： A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.

    摘要翻译： 公开了一种用于交错执行指令的方法和装置。 根据本发明的一个实施例，接收单个宏指令，其中单个宏指令指定至少两个逻辑寄存器，并且其中两个逻辑寄存器分别存储具有相应数据元素的第一和第二压缩数据操作数。 然后，使用相同电路，在来自所述第一和第二打包数据操作数的第一和第二多个相应数据元素上独立地执行由单个宏指令指定的操作，以独立地生成第一和第二多个结果数据元素 。 第一和第二多个结果数据元素作为第三打包数据操作数存储在单个逻辑寄存器中。