公开(公告)号：US08647069B2

公开(公告)日：2014-02-11

申请号：US13171758

申请日：2011-06-29

申请人： Patrick Girard ,  Olivier Kueny ,  Ludovic Pintat ,  Pascal Routier

发明人： Patrick Girard ,  Olivier Kueny ,  Ludovic Pintat ,  Pascal Routier

IPC分类号： F01D5/14 ,  B64C27/46

CPC分类号： F01D5/141 ,  F01D5/225 ,  F05D2250/74 ,  Y02T50/673

摘要： When cold and in the non-coated state, the aerodynamic profile is substantially identical to a nominal profile determined by the Cartesian coordinates X,Y,Z′ given in Table 1, in which the coordinate Z′ is the quotient D/H where D is the distance of the point under consideration from a first reference plane P0 situated at the base of the nominal profile, and H is the height of said profile measured from the first reference plane to a second reference plane P1. The measurements D and H are taken radially relative to the axis of the turbine, while the X coordinate is measured in the axial direction of the turbine.

摘要翻译： 当冷和处于非涂覆状态时，空气动力学特性与由表1中给出的笛卡尔坐标X，Y，Z'确定的标称轮廓基本相同，其中坐标Z'是商D / H，其中D 是从位于标称轮廓底部的第一参考平面P0考虑的点的距离，H是从第一参考平面测量到第二参考平面P1的所述剖面的高度。 测量D和H相对于涡轮机的轴线径向地获得，而X坐标是在涡轮的轴向方向上测量的。

公开(公告)号：US08757983B2

公开(公告)日：2014-06-24

申请号：US13171586

申请日：2011-06-29

申请人： Patrick Girard ,  Olivier Kueny ,  Pierre Marche ,  Ludovic Pintat

发明人： Patrick Girard ,  Olivier Kueny ,  Pierre Marche ,  Ludovic Pintat

IPC分类号： F01D5/14

CPC分类号： F01D5/142 ,  F01D5/141 ,  Y02T50/673

摘要： When cold and in the non-coated state, the aerodynamic profile is substantially identical to a nominal profile determined by the Cartesian coordinates X,Y,Z′ given in Table 1, in which the coordinate Z′ is the quotient D/H where D is the distance of the point under consideration from a first reference plane P0 situated at the base of the nominal profile, and H is the height of said profile measured from the first reference plane to a second reference plane P1. The measurements D and H are taken radially relative to the axis of the turbine, while the X coordinate is measured in the axial direction of the turbine.

摘要翻译： 当冷和处于非涂覆状态时，空气动力学特性与由表1中给出的笛卡尔坐标X，Y，Z'确定的标称轮廓基本相同，其中坐标Z'是商D / H，其中D 是从位于标称轮廓底部的第一参考平面P0考虑的点的距离，H是从第一参考平面测量到第二参考平面P1的所述剖面的高度。 测量D和H相对于涡轮机的轴线径向地获得，而X坐标是在涡轮的轴向方向上测量的。

公开(公告)号：US08734113B2

公开(公告)日：2014-05-27

申请号：US13171561

申请日：2011-06-29

申请人： Patrick Girard ,  Olivier Kueny ,  Renaud Martet ,  Renaud Royan

发明人： Patrick Girard ,  Olivier Kueny ,  Renaud Martet ,  Renaud Royan

IPC分类号： F01D9/02 ,  F01D9/04

CPC分类号： F01D5/141 ,  F01D9/041 ,  F05D2220/321 ,  F05D2220/3215 ,  F05D2240/121 ,  F05D2240/303 ,  Y02T50/673

摘要： When cold and in the non-coated state, the aerodynamic profile is substantially identical to a nominal profile determined by the Cartesian coordinates X,Y,Z′ given in Table 1, in which the coordinate Z′ is the quotient D/H where D is the distance of the point under consideration from a first reference plane P0 situated at the base of the nominal profile, and H is the height of said profile measured from the first reference plane to a second reference plane P1. The measurements D and H are taken radially relative to the axis of the turbine, while the X coordinate is measured in the axial direction of the turbine.

摘要翻译： 当冷和处于非涂覆状态时，空气动力学特性与由表1中给出的笛卡尔坐标X，Y，Z'确定的标称轮廓基本相同，其中坐标Z'是商D / H，其中D 是从位于标称轮廓底部的第一参考平面P0考虑的点的距离，H是从第一参考平面测量到第二参考平面P1的所述剖面的高度。 测量D和H相对于涡轮机的轴线径向地获得，而X坐标是在涡轮的轴向方向上测量的。

公开(公告)号：US20140053635A1

公开(公告)日：2014-02-27

申请号：US13878056

申请日：2011-10-04

申请人： Michel Dos-Reis ,  Michel Bacou ,  Christophe Arruti ,  Patrick Girard

发明人： Michel Dos-Reis ,  Michel Bacou ,  Christophe Arruti ,  Patrick Girard

IPC分类号： G01M3/26

CPC分类号： G01M3/26 ,  B64C13/40 ,  B64C13/48 ,  B64F5/60 ,  F15B19/00 ,  G01M3/007 ,  G01M3/28 ,  G01M3/2815

摘要： A device for testing pneumatic circuits and for measuring the leakage rate from reference pressure lines onboard an aircraft, connected to a plenum chamber. The device includes a multi-pressure system, comprising several sensors each connected to a reference pressure line, first solenoid valves arranged on the input channels to this multi-pressure system, and connected to the reference pressure lines through first connectors, second solenoid valves arranged on the reference pressure lines, a pressure controller module that is connected to all the first solenoid valves through a second connector, an electronic board that controls the solenoid valves and calibration of the multi-pressure system, a control device. The invention also relates to a method making use of this device.

摘要翻译： 一种用于测试气动回路并测量与连接到增压室的飞机上的参考压力管线的泄漏速率的装置。 该装置包括多压力系统，其包括多个传感器，每个传感器各自连接到参考压力管线，第一电磁阀布置在输入通道上并连接到该多压力系统，并通过第一连接器连接到参考压力管线，第二电磁阀设置 在参考压力线上，通过第二连接器连接到所有第一电磁阀的压力控制器模块，控制电磁阀的电子板和多压力系统的校准，控制装置。 本发明还涉及利用该装置的方法。

公开(公告)号：US09418759B2

公开(公告)日：2016-08-16

申请号：US14270555

申请日：2014-05-06

申请人： Nabil Badereddine ,  Leonardo H. Bonet Zordan ,  Patrick Girard ,  Alberto Bosio

发明人： Nabil Badereddine ,  Leonardo H. Bonet Zordan ,  Patrick Girard ,  Alberto Bosio

IPC分类号： G11C29/04 ,  G11C29/12 ,  G11C11/419 ,  G11C29/50 ,  G11C11/41

CPC分类号： G11C29/12 ,  G11C11/41 ,  G11C11/419 ,  G11C29/04 ,  G11C29/50 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2029/5002 ,  G11C2029/5006

摘要： Assist circuits for SRAM memory tests allow voltage scaling in low-power SRAMs. Word line level reduction (WLR) and negative bit line (NBL) boost assist techniques improve read stability and write margin of SRAM core-cells, respectively, when the memory operates at a lowered supply voltage. Assist circuits are activated at particular points in the memory cell circuit. The assist circuits are selectively activated for modifying the voltage along particular circuit elements to identify the potential defects that might be otherwise masked until substantially large. A March test invokes elements for activating the assist circuits to identify defects and indicate functional fault models (FFMs) associated with the defects.

摘要翻译： 用于SRAM存储器测试的辅助电路允许在低功耗SRAM中进行电压调节。 当存储器工作在降低的电源电压时，字线电平降低（WLR）和负位线（NBL）升压辅助技术分别提高SRAM核心单元的读取稳定性和写入裕度。 辅助电路在存储单元电路中的特定点被激活。 辅助电路被选择性地激活以修改沿着特定电路元件的电压，以识别直到基本上大的可能被掩蔽的潜在缺陷。 March测试调用激活辅助电路以识别缺陷的元件，并指出与故障相关的功能故障模型（FFM）。

公开(公告)号：US20150325313A1

公开(公告)日：2015-11-12

申请号：US14270555

申请日：2014-05-06

申请人： Nabil Badereddine ,  Leonardo H. Bonet Zordan ,  Patrick Girard ,  Alberto Bosio

发明人： Nabil Badereddine ,  Leonardo H. Bonet Zordan ,  Patrick Girard ,  Alberto Bosio

IPC分类号： G11C29/04 ,  G11C11/419

CPC分类号： G11C29/12 ,  G11C11/41 ,  G11C11/419 ,  G11C29/04 ,  G11C29/50 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2029/5002 ,  G11C2029/5006

摘要： Assist circuits for SRAM memory tests allow voltage scaling in low-power SRAMs. Word line level reduction (WLR) and negative bit line (NBL) boost assist techniques improve read stability and write margin of SRAM core-cells, respectively, when the memory operates at a lowered supply voltage. Assist circuits are activated at particular points in the memory cell circuit. The assist circuits are selectively activated for modifying the voltage along particular circuit elements to identify the potential defects that might be otherwise masked until substantially large. A March test invokes elements for activating the assist circuits to identify defects and indicate functional fault models (FFMs) associated with the defects.

摘要翻译： 用于SRAM存储器测试的辅助电路允许在低功耗SRAM中进行电压调节。 当存储器工作在降低的电源电压时，字线电平降低（WLR）和负位线（NBL）升压辅助技术分别提高SRAM核心单元的读取稳定性和写入裕度。 辅助电路在存储单元电路中的特定点被激活。 辅助电路被选择性地激活以修改沿着特定电路元件的电压，以识别直到基本上大的可能被掩蔽的潜在缺陷。 March测试调用激活辅助电路以识别缺陷的元件，并指出与缺陷相关的功能故障模型（FFM）。

公开(公告)号：US09147498B2

公开(公告)日：2015-09-29

申请号：US13862513

申请日：2013-04-15

申请人： Leonardo Henrique Bonet Zordan ,  Alberto Bosio ,  Patrick Girard ,  Nabil Badereddine

发明人： Leonardo Henrique Bonet Zordan ,  Alberto Bosio ,  Patrick Girard ,  Nabil Badereddine

IPC分类号： G11C11/00 ,  G11C29/02 ,  G11C29/44 ,  G11C11/41

CPC分类号： G11C29/021 ,  G11C11/41 ,  G11C29/028 ,  G11C29/4401

摘要： A circuit arrangement may include: a memory, composed of a memory cell array, including a plurality of memory cells, and a peripheral circuitry; a voltage source configured to provide at least one supply voltage; a test circuit integrated with the memory cell array and the voltage source, wherein the test circuit receives the supply voltage; the test circuit including: at least one test memory cell; at least one failure detection circuit configured to detect a data retention failure in the at least one test memory cell.

摘要翻译： 电路装置可以包括：包括多个存储器单元的存储单元阵列和外围电路组成的存储器; 电压源，被配置为提供至少一个电源电压; 与存储单元阵列和电压源集成的测试电路，其中测试电路接收电源电压; 所述测试电路包括：至少一个测试存储单元; 至少一个故障检测电路被配置为检测所述至少一个测试存储单元中的数据保留故障。

公开(公告)号：US5916829A

公开(公告)日：1999-06-29

申请号：US616080

申请日：1996-03-14

申请人： Patrick Girard ,  Fred Zeschky

发明人： Patrick Girard ,  Fred Zeschky

IPC分类号： A41C5/00 ,  A41D31/02 ,  D06M17/00 ,  A41C1/08

CPC分类号： A41D31/02 ,  A41C5/00 ,  D06M17/00 ,  Y10T442/3008 ,  Y10T442/3016 ,  Y10T442/3512 ,  Y10T442/3602 ,  Y10T442/40 ,  Y10T442/413

摘要： A fabric laminate (10) comprises first and second stretch fabrics (11 and 12) having an intermediate adhesive securement layer (13) between them. The adhesive securement layer (13) is in the form of a regularly repeated pattern which comprises an array of aligned adhesive elements (14) arranged in successive generally horizontally and vertically extending rows. The array of adhesive elements (14) is capable of offering resistance to elongation as the laminate (10) is subjected to distortion, with the pattern having a differential elongation characterized as offering different magnitudes of resistance to elongation when the fabric laminate (10) is subjected to distortion in selected different directions. The adhesive securement layer (13) is predeterminedly oriented in accordance with its differential elongation and the stretch characteristics of fabrics (11,12) such that the resistance to elongation offered by the laminate (10) is determined by the pattern and orientation of the individual adhesive elements (14) in conjunction with the stretch characteristics of the fabrics (11,12). The laminate (10) may be employed to reinforce items of clothing, particularly underwear and the like.

摘要翻译： 织物层压板（10）包括在它们之间具有中间粘合剂固定层（13）的第一和第二弹性织物（11和12）。 粘合剂固定层（13）是规则重复图案的形式，其包括排列成连续大致水平和垂直延伸的行的排列的粘合元件阵列（14）。 粘合剂元件（14）的阵列能够在叠层（10）受到变形时提供抗延伸性，其中图案具有差异伸长率，其特征在于当织物层压体（10）为 在选定的不同方向进行变形。 粘合固定层（13）根据其不同的伸长率和织物（11,12）的拉伸特性被预定取向，使得由层压体（10）提供的抗拉伸性由单独的图案和取向决定 粘合元件（14）与织物（11,12）的拉伸特性相结合。 层压材料（10）可用于加强衣物，特别是内衣等。

公开(公告)号：US09316561B2

公开(公告)日：2016-04-19

申请号：US13878056

申请日：2011-10-04

申请人： Michel Dos-Reis ,  Michel Bacou ,  Christophe Arruti ,  Patrick Girard

发明人： Michel Dos-Reis ,  Michel Bacou ,  Christophe Arruti ,  Patrick Girard

IPC分类号： G01M3/28 ,  B64F5/00 ,  F15B19/00 ,  G01M3/00 ,  G01M3/26

CPC分类号： G01M3/26 ,  B64C13/40 ,  B64C13/48 ,  B64F5/60 ,  F15B19/00 ,  G01M3/007 ,  G01M3/28 ,  G01M3/2815

摘要： A device for testing pneumatic circuits and for measuring the leakage rate from reference pressure lines onboard an aircraft, connected to a plenum chamber. The device includes a multi-pressure system, comprising several sensors each connected to a reference pressure line, first solenoid valves arranged on the input channels to this multi-pressure system, and connected to the reference pressure lines through first connectors, second solenoid valves arranged on the reference pressure lines, a pressure controller module that is connected to all the first solenoid valves through a second connector, an electronic board that controls the solenoid valves and calibration of the multi-pressure system, a control device. The invention also relates to a method making use of this device.

摘要翻译： 一种用于测试气动回路并测量与连接到增压室的飞机上的参考压力管线的泄漏速率的装置。 该装置包括多压力系统，其包括多个传感器，每个传感器各自连接到参考压力管线，第一电磁阀布置在输入通道上并连接到该多压力系统，并通过第一连接器连接到参考压力管线，第二电磁阀设置 在参考压力线上，通过第二连接器连接到所有第一电磁阀的压力控制器模块，控制电磁阀的电子板和多压力系统的校准，控制装置。 本发明还涉及利用该装置的方法。

公开(公告)号：US20140307515A1

公开(公告)日：2014-10-16

申请号：US13862513

申请日：2013-04-15

申请人： Leonardo Henrique Bonet Zordan ,  Alberto Bosio ,  Patrick Girard ,  Nabil Badereddine

发明人： Leonardo Henrique Bonet Zordan ,  Alberto Bosio ,  Patrick Girard ,  Nabil Badereddine

IPC分类号： G11C29/44

CPC分类号： G11C29/021 ,  G11C11/41 ,  G11C29/028 ,  G11C29/4401

摘要： A circuit arrangement may include: a memory, composed of a memory cell array, including a plurality of memory cells, and a peripheral circuitry; a voltage source configured to provide at least one supply voltage; a test circuit integrated with the memory cell array and the voltage source, wherein the test circuit receives the supply voltage; the test circuit including: at least one test memory cell; at least one failure detection circuit configured to detect a data retention failure in the at least one test memory cell.

摘要翻译： 电路装置可以包括：包括多个存储器单元的存储单元阵列和外围电路组成的存储器; 电压源，被配置为提供至少一个电源电压; 与存储单元阵列和电压源集成的测试电路，其中测试电路接收电源电压; 所述测试电路包括：至少一个测试存储单元; 至少一个故障检测电路被配置为检测所述至少一个测试存储单元中的数据保留故障。