公开(公告)号：US07366179B2

公开(公告)日：2008-04-29

申请号：US10262402

申请日：2002-10-01

申请人： Paul Graves McElroy ,  Phillip Stone Herron ,  Bruce Edward Mitchell ,  Darrin Leroy Gieger

发明人： Paul Graves McElroy ,  Phillip Stone Herron ,  Bruce Edward Mitchell ,  Darrin Leroy Gieger

IPC分类号： H04L12/56

CPC分类号： H04L49/3081 ,  H04L49/20 ,  H04L49/30 ,  H04L2012/5671

摘要： A dual PHY-based integrated access device (IAD) platform employs a highly integrated time division multiplexed (TDM), a synchronous transfer mode (ATM) cell based architecture, to provide enhanced interfacing flexibility for multiple and diverse signaling protocols, effectively reducing the cost and constraints as to choice of host processor used in conventional digital signal processor (DSP)-based IADs. With the signaling transport speed of the dual PHY based path being an order of magnitude greater than that of any of the plurality of communication paths with which the IAD is interfaced, the IAD of the invention provides effectively real time support for different communication requirements, including TDM, ATM, HDLC, and the like.

摘要翻译： 基于双PHY的集成接入设备（IAD）平台采用高度集成的时分复用（TDM），基于同步传输模式（ATM）小区的架构，为多种和多种信令协议提供增强的接口灵活性，有效降低成本 以及用于在基于传统数字信号处理器（DSP）的IAD中使用的主处理器的选择的约束。 由于基于双PHY的路径的信令传输速度比IAD接口的多个通信路径的信令传输速度大一个数量级，所以本发明的IAD可有效地为不同的通信要求提供实时支持，包括 TDM，ATM，HDLC等。

公开(公告)号：US07061916B2

公开(公告)日：2006-06-13

申请号：US10095380

申请日：2002-03-12

申请人： Phillip Stone Herron ,  Bruce Edward Mitchell

发明人： Phillip Stone Herron ,  Bruce Edward Mitchell

IPC分类号： H04J3/24 ,  H04L12/66 ,  G06F15/173

CPC分类号： H04Q11/0478 ,  H04L2012/561 ,  H04L2012/5656 ,  H04L2012/5671 ,  H04L2012/5681

摘要： A voice path direct memory access (DMA)-based packet generation mechanism writes digitally encoded voice samples directly into prescribed subportions of a preallocated portion of random access memory, to avoid interrupting a main processor for the purpose. A pointer to a respective buffer space subportion is presented to a protocol stack, so that one or more overhead bytes for the stored voice samples can be generated and written into adjacent address space of the preallocated portion of random access memory. The contents of the preallocated memory space are then serialized out for transmission to a destination receiver.

公开(公告)号：US08948604B1

公开(公告)日：2015-02-03

申请号：US12978854

申请日：2010-12-27

申请人： Leif J. Sandstrom ,  Phillip Stone Herron

发明人： Leif J. Sandstrom ,  Phillip Stone Herron

IPC分类号： H04B10/00

CPC分类号： H04B10/564 ,  H04B10/40 ,  H04B10/6911

摘要： The present disclosure generally pertains to optical communication apparatuses having field-tunable power characteristics. In one exemplary embodiment, an optical communication apparatus has an optical transmitter. The optical transmitter is coupled to logic that receives a user input indicative of a desired transmit mode for the transmitter, and the logic then dynamically tunes the transmitter's output power according to the selected transmit mode. In addition, the optical communication apparatus may have an optical receiver for receiving optical signals. The sensitivity of the receiver is controlled by a bias voltage that is applied to the receiver by the logic. The logic is configured to receive a user input indicative of a desired receive mode and then to tune the receiver's sensitivity via the bias voltage according to the selected receive mode. Accordingly, both the transmitter and receiver of an optical communication apparatus can be tuned in the field to operate in a desired range, and a field technician can therefore utilize the same optical communication apparatus in any of a variety of applications.

摘要翻译： 本公开通常涉及具有场可调功率特性的光通信设备。 在一个示例性实施例中，光通信设备具有光发射机。 光发射机被耦合到逻辑，其接收指示发射机的期望发射模式的用户输入，然后该逻辑根据选择的发射模式动态地调谐发射机的输出功率。 此外，光通信装置可以具有用于接收光信号的光接收机。 接收器的灵敏度由通过逻辑施加到接收器的偏置电压来控制。 逻辑被配置为接收指示期望接收模式的用户输入，然后根据所选择的接收模式经由偏置电压来调整接收机的灵敏度。 因此，光通信装置的发射机和接收机都可以在现场进行调谐以在期望的范围内操作，因此现场技术人员可以在各种应用中的任何一种中使用相同的光通信装置。

公开(公告)号：US07076631B2

公开(公告)日：2006-07-11

申请号：US10412854

申请日：2003-04-14

申请人： Phillip Stone Herron

发明人： Phillip Stone Herron

IPC分类号： G06F12/00

CPC分类号： G06F9/30043 ,  G06F9/3017 ,  G06F9/32 ,  G06F9/3863

摘要： Unaligned accesses to memory are circumvented by an address exception handler mechanism, which decodes an exception-triggering instruction, and reads from or writes to, in a byte-by-byte manner, addressed portions of memory which are unaligned with an addressing scheme through which accesses to memory may be performed, and thereby give rise to unaligned memory access exceptions. The handler simulates the execution of the instruction with reference to an exception stack frame, to which the contents of all registers at the time of the unaligned address exception are saved. This allows the handler to controllably define values that are restored into registers during the processor's execution of a general exception vector. After handling the exception, program execution transitions to the next instruction that directly follows the exception-causing instruction.

摘要翻译： 通过地址异常处理机制解决了对存储器的不对齐访问，该机制解码异常触发指令，并以逐个字节的方式读取或写入与寻址方案不一致的存储器的寻址部分， 可以执行对存储器的访问，从而引起不对齐的存储器访问异常。 处理程序参照异常堆栈帧模拟指令的执行，保存未对齐地址异常时所有寄存器的内容。 这允许处理程序可控地定义在处理器执行一般异常向量期间恢复为寄存器的值。 在处理异常之后，程序执行转换到直接跟随引发异常指令的下一条指令。

公开(公告)号：US07545828B2

公开(公告)日：2009-06-09

申请号：US10408590

申请日：2003-04-07

申请人： Phillip Stone Herron

发明人： Phillip Stone Herron

IPC分类号： H04J3/22

CPC分类号： H04L49/3081 ,  H04L49/20 ,  H04L49/30 ,  H04L2012/5671

摘要： A mechanism for implementing a single-interrupt-based voice playout buffer transfer operation. The contents of each respective channel of a multi-channel voice playout buffer are encapsulated so as to prepend a four byte ATM header, a HEC byte, and a four byte AAL2 header to a forty-four byte voice channel field to realize a standard fifty-three byte ATM cell. Within the AAL2 header, a channel identification byte (CID) provides selective mapping to timeslots of a TDM frame, to accommodate variations among different vendor equipments. The next to last bit of the last byte of the ATM header is used as an interrupt to the network processor. Only the highest voice channel asserts this next to last bit as an interrupt bit.

摘要翻译： 一种用于实现基于单中断的语音播放缓冲器传送操作的机制。 多声道语音播出缓冲器的每个通道的内容被封装，以便在四十四字节的话音信道字段前面加上一个四字节的ATM头，一个HEC字节和一个四字节的AAL2头，以实现标准的五十 三字节ATM信元。 在AAL2报头内，信道标识字节（CID）提供对TDM帧的时隙的选择性映射，以适应不同供应商设备之间的变化。 ATM头的最后一个字节的最后一位的下一个被用作网络处理器的中断。 只有最高的语音通道才将最后一位作为中断位置位。

公开(公告)号：US07289532B2

公开(公告)日：2007-10-30

申请号：US10441091

申请日：2003-05-19

申请人： Darrin L. Gieger ,  Phillip Stone Herron ,  Dennis B. McMahan

发明人： Darrin L. Gieger ,  Phillip Stone Herron ,  Dennis B. McMahan

IPC分类号： H04J3/16

CPC分类号： H04L49/3081 ,  H04L49/20 ,  H04L49/30 ,  H04L2012/5671

摘要： A voice playout buffer for a dual PHY-based integrated access device platform has a plurality of voice signal buffer sections. A respective buffer section has a capacity in excess of the number of digitized voice signal bytes contained in a respective cell-based communication signal. The storage capacity of a buffer section accommodates a communications control processor writing new outgoing digitized voice signal bytes into the first portion of the voice signal buffer section for transport over a TDM communication link, prior to digitized voice signals newly received from the TDM communication link being written into the first portion of the voice signal buffer section.

摘要翻译： 用于基于双PHY的集成接入设备平台的语音播出缓冲器具有多个语音信号缓冲器部分。 相应的缓冲器部分具有超过相应的基于单元的通信信号中包含的数字化语音信号字节的数量的容量。 缓冲器部分的存储容量容纳通信控制处理器，其将新的输出数字化语音信号字节写入到语音信号缓冲器部分的第一部分中，以便在从TDM通信链路新接收的数字化语音信号之前通过TDM通信链路进行传输， 写入语音信号缓冲器部分的第一部分。