利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

5 条记录 (耗时 0.02 秒)

    Semiconductor memory system and semiconductor memory chip
    1.
    发明申请
    Semiconductor memory system and semiconductor memory chip 有权
    半导体存储器系统和半导体存储器芯片

    公开(公告)号：US20070047372A1

    公开(公告)日：2007-03-01

    申请号：US11509092

    申请日：2006-08-24

    申请人： Paul Wallner ,  Andre Schafer ,  Peter Gregorius

    发明人： Paul Wallner ,  Andre Schafer ,  Peter Gregorius

    IPC分类号： G11C8/00

    CPC分类号： G11C8/12 ,  G11C7/1051 ,  G11C2207/107

    摘要： A semiconductor memory system includes a semiconductor memory chip in which data, command, and address signals are transmitted serially between a memory controller and the semiconductor memory chip in signal frames in correspondence with a predetermined protocol. In a receive signal path within the semiconductor memory chip, a frame decoder for decoding the signal frames is arranged following a receiving interface device, and between the frame decoder and a memory core, an intermediate storage device is arranged which has a cell array including a multiplicity of memory cells, and an addressing and selector circuit to which address signals decoded by the frame decoder from command and/or write signal frames supplied by the memory controller are applied, for addressing the cell array and for selecting the write data to be written into the cell array and to be read out of the cell array.

    摘要翻译： 半导体存储器系统包括半导体存储器芯片，其中数据，命令和地址信号在与预定协议相对应的信号帧中的存储器控​​制器和半导体存储器芯片之间串行发送。 在半导体存储器芯片内的接收信号路径中，用于对信号帧进行解码的帧解码器被布置在接收接口设备之后，并且在帧解码器和存储器核心之间，布置中间存储设备，其具有包括单元阵列 多个存储器单元，以及寻址和选择器电路，由帧解码器从由存储器控制器提供的命令和/或写入信号帧解码的地址信号被应用于寻址单元阵列并用于选择要写入的写入数据 进入单元阵列并从单元阵列中读出。

    Method and device for transmission of adjustment information for data interface drivers for a RAM module
    2.
    发明申请
    Method and device for transmission of adjustment information for data interface drivers for a RAM module 有权
    用于传输用于RAM模块的数据接口驱动程序的调整信息的方法和装置

    公开(公告)号：US20070064509A1

    公开(公告)日：2007-03-22

    申请号：US11384811

    申请日：2006-03-21

    申请人： Andre Schafer

    发明人： Andre Schafer

    IPC分类号： G11C29/00

    CPC分类号： G11C7/1057 ,  G11C7/1027 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1084 ,  G11C2207/2254

    摘要： A method and a device are described for transmission of control information for the adjustment of operating parameters of drivers in the data interface of a RAM module by means of a controller, with control bits for adjustment purposes being sent during an adjustment mode by the controller as a burst of data bits at the data clock rate to the RAM module. According to the invention, each control bit which is sent from the controller via the data channel in the burst is represented by a sequence of n≧2 data bits, which have a binary value corresponding to the relevant control bit and follow one another at the data clock rate. The binary value of each control bit sent via the data channel is determined in the RAM module by detection of the binary value of the sent burst within the relevant sequence at a time at which the m-th data bit in the sequence appears, where m>1.

    摘要翻译： 描述了一种方法和装置，用于传输用于通过控制器调整RAM模块的数据接口中的驱动器的操作参数的控制信息，其中调节目的的控制位在控制器的调整模式期间被发送 以RAM模块的数据时钟速率的数据位脉冲串。 根据本发明，通过脉冲串中的数据信道从控制器发送的每个控制位由n> = 2数据位的序列表示，其具有对应于相关控制位的二进制值并且彼此相关 数据时钟速率。 通过数据通道发送的每个控制位的二进制值在RAM模块中通过在序列中出现第m个数据位的时间检测相关序列内的发送脉冲串的二进制值来确定，其中m > 1。

    Memory component with improved noise insensitivity
    4.
    发明申请
    Memory component with improved noise insensitivity 有权
    具有改善噪声不敏感性的存储器组件

    公开(公告)号：US20050179492A1

    公开(公告)日：2005-08-18

    申请号：US11031740

    申请日：2005-01-07

    申请人： Andre Schafer

    发明人： Andre Schafer

    IPC分类号： G11C5/14 ,  G11C7/00 ,  G11C7/02 ,  G11C7/10 ,  G11C11/4063 ,  H03F1/26 ,  H03F3/45

    CPC分类号： H03F3/45475 ,  G11C11/4074 ,  H03F1/26

    摘要： A memory component comprises a memory cell array, signal inputs, input amplifiers connected to respective ones of the signal inputs, for receiving, amplifying and outputting data, address or control signals, a data, address or control signal generator for the memory cell array, a first supply network for supplying power to the input amplifiers and a second supply network for supplying power to the data, address or control signal generator, wherein the first supply network and the second supply network do not have a direct connection.

    摘要翻译： 存储器组件包括存储单元阵列，信号输入，连接到相应信号输入端的输入放大器，用于接收，放大和输出数据，地址或控制信号，用于存储单元阵列的数据，地址或控制信号发生器， 用于向输入放大器供电的第一供电网络和用于向数据，地址或控制信号发生器供电的第二供电网络，其中第一供电网络和第二供电网络不具有直接连接。

    Method for setting a termination voltage and an input circuit
    5.
    发明申请
    Method for setting a termination voltage and an input circuit 失效
    用于设置终端电压和输入电路的方法

    公开(公告)号：US20050001650A1

    公开(公告)日：2005-01-06

    申请号：US10831623

    申请日：2004-04-23

    申请人： Andre Schafer

    发明人： Andre Schafer

    IPC分类号： G05F1/575 ,  H03K5/007 ,  H04L25/02 ,  H04L25/06 ,  H03K17/16

    CPC分类号： H04L25/0292 ,  G05F1/575 ,  H03K5/007 ,  H04L25/063

    摘要： Input circuit and method for setting a termination voltage. One embodiment provides a method for setting a termination voltage of an input circuit of an integrated circuit, the input circuit having an input terminal for receiving a signal, the termination voltage being applied to the input terminal, the received signal being driven with respect to the termination voltage and being evaluated by a comparison with a reference potential, the termination voltage being generated and being set in accordance with a control signal, the control signal being generated in a manner dependent on a comparison of one or more signal levels of the received signal with an assessment potential, the termination voltage being set by means of the control signal in such a way that the reliability of the signal reception is maximized.

    摘要翻译： 输入电路和设定端接电压的方法。 一个实施例提供了一种用于设置集成电路的输入电路的终端电压的方法，该输入电路具有用于接收信号的输入端子，终端电压被施加到输入端子，所接收的信号相对于 终止电压并通过与参考电位进行比较来评估，所述终止电压是根据控制信号产生和设定的，所述控制信号以取决于接收信号的一个或多个信号电平的比较的方式产生 具有评估电位，终端电压通过控制信号设置，使得信号接收的可靠性最大化。