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    Balanced-delay programmable logic array and method for balancing programmable logic array delays
    2.
    发明授权
    Balanced-delay programmable logic array and method for balancing programmable logic array delays 有权
    平衡延迟可编程逻辑阵列和平衡可编程逻辑阵列延迟的方法

    公开(公告)号：US06294929B1

    公开(公告)日：2001-09-25

    申请号：US09443205

    申请日：1999-11-18

    申请人： Paula Kristine Coulman ,  Sang Hoo Dhong ,  Jaehong Park ,  Stephen Douglas Posluszny ,  Osamu Takahashi

    发明人： Paula Kristine Coulman ,  Sang Hoo Dhong ,  Jaehong Park ,  Stephen Douglas Posluszny ,  Osamu Takahashi

    IPC分类号： H03K19177

    CPC分类号： H03K19/17712

    摘要： Balanced-delay programmable logic array and a method for balancing programmable logic array delays provide improved performance in circuits employing programmable logic. By adding transistors to the programming plane that do not form part of the logic implementation, the capacitance on each of the input logic lines can be balanced, substantially reducing the skew between signals entering the final logic gates. This provides programmable logic arrays that may implement asynchronous logic in applications where skew was previously prohibitive and further increases the reliability of state evaluations in synchronous logic.

    摘要翻译： 平衡延迟可编程逻辑阵列和用于平衡可编程逻辑阵列延迟的方法在采用可编程逻辑的电路中提供改进的性能。 通过将晶体管添加到不构成逻辑实现的一部分的编程平面，可以平衡每个输入逻辑线上的电容，从而大大减少进入最终逻辑门的信号之间的偏移。 这提供了可编程逻辑阵列，可以在以前禁止偏移的应用中实现异步逻辑，并进一步提高了同步逻辑中的状态评估的可靠性。

    Self-resetting circuit timing correction
    3.
    发明授权
    Self-resetting circuit timing correction 失效
    自复位电路定时校正

    公开(公告)号：US06232798B1

    公开(公告)日：2001-05-15

    申请号：US09457938

    申请日：1999-12-09

    申请人： Paula Kristine Coulman ,  Sang Hoo Dhong ,  Joel Abraham Silberman ,  Osamu Takahashi

    发明人： Paula Kristine Coulman ,  Sang Hoo Dhong ,  Joel Abraham Silberman ,  Osamu Takahashi

    IPC分类号： H03K1900

    CPC分类号： H03K19/0966

    摘要： A system and method with a self-reset circuit for synchronizing an input data path with a timing control path. The self-resetting circuit includes a normal-mode input detect circuit which detects an arrival of data from the input data path into the self-reset circuit and generates a normal-mode control signal in response thereto. The self-resetting circuit also includes a delay-mode input detect circuit for detecting the arrival of the data from the input data path and which generates a delay-mode control signal in response thereto. A toggle circuit is provided for disabling the normal-mode input detect circuit while simultaneously enabling the delay-mode input detect circuit. In response to the toggle circuit disabling the normal-mode input detect circuit, the delay-mode control signal propagates through a delay gate, such that said delay-mode control signal synchronizes said timing control path with respect to said data input path.

    摘要翻译： 一种具有用于使输入数据路径与定时控制路径同步的自复位电路的系统和方法。 自复位电路包括正常模式输入检测电路，其检测数据从输入数据路径到达自复位电路，并响应于此产生正常模式控制信号。 自复位电路还包括延迟模式输入检测电路，用于检测来自输入数据路径的数据的到达并响应于此生成延迟模式控制信号。 提供了一种切换电路，用于在同时使能延迟模式输入检测电路的同时禁用正常模式输入检测电路。 响应于切换电路禁用正常模式输入检测电路，延迟模式控制信号通过延迟门传播，使得所述延迟模式控制信号使所述定时控制路径相对于所述数据输入路径同步。