公开(公告)号：US08347259B1

公开(公告)日：2013-01-01

申请号：US13193721

申请日：2011-07-29

Applicant: Pavan Y. Bashaboina ,  James A. Culp

Inventor： Pavan Y. Bashaboina ,  James A. Culp

IPC: G06F17/50

CPC classification number: G06F17/5068

Abstract: Critical circuit blocks are identified in a chip design layout, and are marked by a marker layer identifying a marked region. Multiplicate layers are generated for each critical circuit block within each marked region. Each multiplicate layer includes a different type of variant for each identified critical circuit block. The different types of variants correspond to different types of optimization goals to address different issues in circuit performance. Circuit simulation is performed with each type of variants in combination with adjacent circuit blocks as provided in original design. In each marked region, the results of the circuit simulations are evaluated to determine an optimal type among the variants. The optimal type is retained in each marked region, thereby providing a chip design layout in which various marked regions can include different types of variant circuit blocks to provide local circuit optimization.

Abstract translation: 关键电路块以芯片设计布局标识，并标记标识区域的标记层。 为每个标记区域内的每个关键电路块生成多重层。 每个多重层包括用于每个识别的关键电路块的不同类型的变体。 不同类型的变体对应于不同类型的优化目标，以解决电路性能中的不同问题。 在原始设计中提供的每种类型的变体与相邻电路块的组合进行电路仿真。 在每个标记区域中，评估电路模拟的结果以确定变体中的最佳类型。 最佳类型保留在每个标记区域中，从而提供芯片设计布局，其中各种标记区域可以包括不同类型的变体电路块以提供本地电路优化。

公开(公告)号：US08458625B2

公开(公告)日：2013-06-04

申请号：US13193716

申请日：2011-07-29

Applicant: Pavan Y. Bashaboina ,  James A. Culp

Inventor： Pavan Y. Bashaboina ,  James A. Culp

IPC: G06F17/50

CPC classification number: G03F7/70433 ,  G03F7/705

Abstract: Potential lithographic hot spots associated with a lithographic level are marked by a marker layer identifying a marked region. Multiplicate layers are generated for each design shape in that lithographic level in each marked region. Each multiplicate layer includes a different type of variant for each design shape in the lithographic level. The different types of variants correspond to different design environments. Lithographic simulation is performed with each type of variants under the constraint of long range effects, such as pattern density, provided by adjacent shapes in the lithographic level. In each marked region, the results of lithographic simulations are evaluated to determine an optimal type among the variants. The optimal type is retained for the lithographic level in each marked region, thereby providing a chip design layout in which various marked regions can include different types of variant shapes to provide local lithographic optimization.

Abstract translation: 与光刻层相关的潜在平版印刷热点由识别标记区域的标记层标记。 为每个标记区域中的光刻级别中的每个设计形状生成多重层。 每个多重层包括在光刻层级中的每个设计形状的不同类型的变体。 不同类型的变体对应于不同的设计环境。 在长距离效应的约束下，每种类型的变体进行平版印刷模拟，例如由光刻层面中的相邻形状提供的图案密度。 在每个标记区域中，评估光刻模拟的结果以确定变体中的最佳类型。 为每个标记区域中的光刻级别保留最佳类型，从而提供芯片设计布局，其中各种标记区域可以包括不同类型的变体形状以提供局部光刻优化。

公开(公告)号：US20130031519A1

公开(公告)日：2013-01-31

申请号：US13193716

申请日：2011-07-29

Applicant: Pavan Y. Bashaboina ,  James A. Culp

Inventor： Pavan Y. Bashaboina ,  James A. Culp

IPC: G06F17/50

CPC classification number: G03F7/70433 ,  G03F7/705

Abstract: Potential lithographic hot spots associated with a lithographic level are marked by a marker layer identifying a marked region. Multiplicate layers are generated for each design shape in that lithographic level in each marked region. Each multiplicate layer includes a different type of variant for each design shape in the lithographic level. The different types of variants correspond to different design environments. Lithographic simulation is performed with each type of variants under the constraint of long range effects, such as pattern density, provided by adjacent shapes in the lithographic level. In each marked region, the results of lithographic simulations are evaluated to determine an optimal type among the variants. The optimal type is retained for the lithographic level in each marked region, thereby providing a chip design layout in which various marked regions can include different types of variant shapes to provide local lithographic optimization.

Abstract translation: 与光刻层相关的潜在平版印刷热点由识别标记区域的标记层标记。 为每个标记区域中的光刻级别中的每个设计形状生成多重层。 每个多重层包括在光刻层级中的每个设计形状的不同类型的变体。 不同类型的变体对应于不同的设计环境。 在长距离效应的约束下，每种类型的变体进行平版印刷模拟，例如由光刻层面中的相邻形状提供的图案密度。 在每个标记区域中，评估光刻模拟的结果以确定变体中的最佳类型。 为每个标记区域中的光刻级别保留最佳类型，从而提供芯片设计布局，其中各种标记区域可以包括不同类型的变体形状以提供局部光刻优化。

公开(公告)号：US20120144354A1

公开(公告)日：2012-06-07

申请号：US12958979

申请日：2010-12-02

Applicant: Pavan Y. Bashaboina ,  Brent A. Goplen ,  Howard S. Landis

Inventor： Pavan Y. Bashaboina ,  Brent A. Goplen ,  Howard S. Landis

IPC: G06F17/50

CPC classification number: G06F17/5072

Abstract: Variation of a parameter of interest is reduced over a field of interest in, for example, an object design, such as a circuit design. The field of interest is divided into tiles. A parameter value is found for each tile and for a group of tiles around each tile. Using these values, variation of the parameter is determined. An adjusted value of the parameter for each tile is determined taking limits into account, iterating until variation is below a threshold value. Parameter uniformity is improved in some applications by over 30% with runtime reduced by an order of magnitude.

Abstract translation: 感兴趣的参数的变化在诸如电路设计的对象设计之类的感兴趣领域中减少。 感兴趣的领域分为瓷砖。 为每个图块和每个图块周围的一组图块找到一个参数值。 使用这些值，确定参数的变化。 确定每个瓦片的参数的调整值，考虑到限制，迭代直到变化低于阈值。 在一些应用中，参数均匀性得到改善，超过30％，运行时间减少一个数量级。

公开(公告)号：US08954901B2

公开(公告)日：2015-02-10

申请号：US12958979

申请日：2010-12-02

Applicant: Pavan Y. Bashaboina ,  Brent A. Goplen ,  Howard S. Landis

Inventor： Pavan Y. Bashaboina ,  Brent A. Goplen ,  Howard S. Landis

IPC: G06F17/50

CPC classification number: G06F17/5072

Abstract: Variation of a parameter of interest is reduced over a field of interest in, for example, an object design, such as a circuit design. The field of interest is divided into tiles. A parameter value is found for each tile and for a group of tiles around each tile. Using these values, variation of the parameter is determined. An adjusted value of the parameter for each tile is determined taking limits into account, iterating until variation is below a threshold value. Parameter uniformity is improved in some applications by over 30% with runtime reduced by an order of magnitude.

Abstract translation: 感兴趣的参数的变化在诸如电路设计的对象设计之类的感兴趣领域中减少。 感兴趣的领域分为瓷砖。 为每个图块和每个图块周围的一组图块找到一个参数值。 使用这些值，确定参数的变化。 确定每个瓦片的参数的调整值，考虑到限制，迭代直到变化低于阈值。 在一些应用中，参数均匀性得到改善，超过30％，运行时间减少一个数量级。